- 专利标题： SEMICONDUCTOR WAFER SCRIBELANE STRUCTURE
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申请号： US17833380申请日： 2022-06-06
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公开(公告)号： US20230282595A1公开(公告)日： 2023-09-07
- 发明人: Jeffrey Alan West , Elizabeth Costner Stewart
- 申请人： TEXAS INSTRUMENTS INCORPORATED
- 申请人地址： US TX Dallas
- 专利权人： TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人： TEXAS INSTRUMENTS INCORPORATED
- 当前专利权人地址： US TX Dallas
- 主分类号： H01L23/544
- IPC分类号： H01L23/544 ; H01L21/78
摘要：
An integrated circuit (IC) fabrication flow including a multilevel metallization scheme wherein one or more metal layer members of a scribelane structure are formed according to one or more design constraints. A total thickness of the metal layer members of the scribelane structure along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.
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