-
1.发明公开公开(公告)号：US20240112953A1
公开(公告)日：2024-04-04
申请号：US18148231
申请日：2022-12-29
发明人： Jeffrey Alan West , Elizabeth Costner Stewart , Thomas Dyer Bonifield , Byron Lovell Williams , Kashyap Barot , Viresh Chinchansure , Sreeram N S
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L21/76877 , H01L21/76816 , H01L23/5226 , H01L23/528
摘要： A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.
-
公开(公告)号：US11881449B2
公开(公告)日：2024-01-23
申请号：US16916748
申请日：2020-06-30
IPC分类号： H01L23/522 , H01L23/58 , H01L23/64 , H01L27/01
CPC分类号： H01L23/5223 , H01L23/5227 , H01L23/585
摘要： An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.
-
公开(公告)号：US20230197634A1
公开(公告)日：2023-06-22
申请号：US17558017
申请日：2021-12-21
CPC分类号： H01L23/562 , H01L23/585 , H01L28/10
摘要： An integrated circuit with a first conductive region, a second conductive region, a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region, and at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type. Each dielectric layer of a first material type has a thickness in a range from 0.5 μm to 5.0 μm, and the at least one dielectric layer of a second material type is not contacting a metal and has a thickness less than 2.0 μm, and the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.
-
公开(公告)号：US11205695B2
公开(公告)日：2021-12-21
申请号：US15850999
申请日：2017-12-21
发明人： Elizabeth C. Stewart , Jeffrey Alan West , Thomas D. Bonifield , Jay Sung Chun , Byron Lovell Williams
IPC分类号： H01L21/02 , H01L23/522 , H01L49/02 , H01L21/027 , H01L21/311
摘要： Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.
-
公开(公告)号：US10998278B2
公开(公告)日：2021-05-04
申请号：US16832356
申请日：2020-03-27
摘要： A microelectronic device contains a high voltage component having an upper plate and a lower plate. The upper plate is isolated from the lower plate by a main dielectric between the upper plate and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the upper plate and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer of silicon nitride having a refractive index between 2.11 and 2.23. The lower-bandgap dielectric layer extends beyond the upper plate continuously around the upper plate. The lower-bandgap dielectric layer has an isolation break surrounding the upper plate at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the upper plate.
-
公开(公告)号：US20190198604A1
公开(公告)日：2019-06-27
申请号：US15850999
申请日：2017-12-21
发明人： Elizabeth C. Stewart , Jeffrey Alan West , Thomas D. Bonifield , Jay Sung Chun , Byron Lovell Williams
IPC分类号： H01L49/02 , H01L21/027 , H01L21/311 , H01L21/02 , H01L23/522
CPC分类号： H01L28/40 , H01L21/02164 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/0274 , H01L21/31116 , H01L21/31144 , H01L23/5223
摘要： Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.
-
7.发明申请HIGH BREAKDOWN VOLTAGE MICROELECTRONIC DEVICE ISOLATION STRUCTURE WITH IMPROVED RELIABILITY 有权具有改进可靠性的高突破电压微电子器件隔离结构公开(公告)号：US20150333055A1
公开(公告)日：2015-11-19
申请号：US14277851
申请日：2014-05-15
CPC分类号： H01L28/91 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/823481 , H01L27/0629 , H01L28/40 , H01L28/60 , H01L29/0692 , H01L29/66477 , H01L29/78 , H01L29/7833
摘要： A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low voltage node by a main dielectric between the high voltage node and low voltage elements at a surface of the substrate of the microelectronic device. A lower-bandgap dielectric layer is disposed between the high voltage node and the main dielectric. The lower-bandgap dielectric layer contains at least one sub-layer with a bandgap energy less than a bandgap energy of the main dielectric. The lower-bandgap dielectric layer extends beyond the high voltage node continuously around the high voltage node. The lower-bandgap dielectric layer has an isolation break surrounding the high voltage node at a distance of at least twice the thickness of the lower-bandgap dielectric layer from the high voltage node.
摘要翻译： 微电子器件包含具有高电压节点和低电压节点的高电压分量。 高电压节点通过微电子器件的基板的表面处的高压节点和低电压元件之间的主电介质与低电压节点隔离。 低压隙电介质层设置在高电压节点和主电介质之间。 低带隙电介质层含有至少一个带隙能量小于主电介质带隙能量的子层。 低带隙电介质层围绕高压节点连续延伸超过高压节点。 较低带隙电介质层具有围绕高电压节点的隔离断裂，距离高压节点的至少两倍于低带隙电介质层的厚度。
-
公开(公告)号：US20240120367A1
公开(公告)日：2024-04-11
申请号：US18390395
申请日：2023-12-20
IPC分类号： H01G4/30 , H01L23/00 , H01L23/495 , H01L25/16
CPC分类号： H01L28/60 , H01L23/49575 , H01L24/05 , H01L25/16 , H01L2224/0556 , H01L2224/05624
摘要： An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.
-
公开(公告)号：US20240113095A1
公开(公告)日：2024-04-04
申请号：US18067703
申请日：2022-12-17
CPC分类号： H01L27/01 , H01L21/0214 , H01L21/02247 , H01L21/02252 , H01L23/3157 , H01L24/05 , H01L24/06 , H01L2224/05567 , H01L2224/06102
摘要： A microelectronic device including an isolation device with a stabilized dielectric. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The dielectric sidewall of the inorganic dielectric plateau is stabilized in a nitrogen containing plasma which forms a SiOxNy surface on the dielectric sidewall of the inorganic dielectric plateau. The SiOxNy surface on the dielectric sidewall of the inorganic dielectric plateau reduces ingress of moisture into the dielectric stack of the inorganic dielectric plateau.
-
公开(公告)号：US20240112852A1
公开(公告)日：2024-04-04
申请号：US17957875
申请日：2022-09-30
发明人： Jeffrey Alan West , Byron Lovell Williams , Kashyap Barot , Sreeram N. S. , Viresh Chinchansure
CPC分类号： H01F27/324 , H01F41/122 , H01F2027/329
摘要： A microelectronic device includes a galvanic isolation component. The galvanic isolation component includes a lower winding and an upper isolation element over the lower winding. The galvanic isolation component further includes a field suppression structure located interior to the lower winding. The field suppression structure includes a conductive field deflector that is separated from the lower winding by a lateral distance that is half a thickness of the lower winding to twice the thickness of the lower winding. A top surface of the conductive field deflector is substantially coplanar with a bottom surface of the lower winding. The conductive field deflector is electrically connected to a semiconductor material in a substrate. The lower winding is separated from a substrate by a first dielectric layer. The upper isolation element is separated from the lower winding by a second dielectric layer.
-
-
-
-
-
-
-
-
-
搜索结果
63 条记录 (耗时 0.02 秒)
