Invention Publication
- Patent Title: SYNCHRONOUS MICROTHREADING
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Application No.: US17712120Application Date: 2022-04-02
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Publication No.: US20230315458A1Publication Date: 2023-10-05
- Inventor: Shreesha SRINATH , Jonathan PEARCE , David B. SHEFFIELD , Ching-Kai LIANG , Jeffrey COOK
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F9/30
- IPC: G06F9/30

Abstract:
Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.
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