-
公开(公告)号：US20230315460A1
公开(公告)日：2023-10-05
申请号：US17712129
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/3009 , G06F9/30094
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
-
公开(公告)号：US20230315455A1
公开(公告)日：2023-10-05
申请号：US17712118
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3009 , G06F9/30105 , G06F9/30043 , G06F9/30047
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
-
公开(公告)号：US20230315458A1
公开(公告)日：2023-10-05
申请号：US17712120
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： Shreesha SRINATH , Jonathan PEARCE , David B. SHEFFIELD , Ching-Kai LIANG , Jeffrey COOK
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/30065 , G06F9/3009
Abstract: Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.
-
公开(公告)号：US20250068588A1
公开(公告)日：2025-02-27
申请号：US18822815
申请日：2024-09-03
Applicant: Intel Corporation
Inventor： Joydeep RAY , Aravindh ANANTARAMAN , Abhishek R. APPU , Altug KOKER , Elmoustapha OULD-AHMED-VALL , Valentin ANDREI , Subramaniam MAIYURAN , Nicolas GALOPPO VON BORRIES , Varghese GEORGE , Mike MACPHERSON , Ben ASHBAUGH , Murali RAMADOSS , Vikranth VEMULAPALLI , William SADLER , Jonathan PEARCE , Sungye KIM
Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20230315572A1
公开(公告)日：2023-10-05
申请号：US17712121
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
CPC classification number: G06F11/1405 , G06F9/3861 , G06F15/7889 , G06F9/3009 , G06F9/226
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
-
Patent Agency Ranking
公开(公告)号：US20230315459A1
公开(公告)日：2023-10-05
申请号：US17712122
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/3009 , G06F9/3013
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
-
公开(公告)号：US20230315445A1
公开(公告)日：2023-10-05
申请号：US17712126
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
CPC classification number: G06F9/223 , G06F9/30101 , G06F9/3009
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
-
公开(公告)号：US20240045830A1
公开(公告)日：2024-02-08
申请号：US18450685
申请日：2023-08-16
Applicant: Intel Corporation
Inventor： Joydeep RAY , Aravindh ANANTARAMAN , Abhishek R. APPU , Altug KOKER , Elmoustapha OULD-AHMED-VALL , Valentin ANDREI , Subramaniam MAIYURAN , Nicolas GALOPPO VON BORRIES , Varghese GEORGE , Mike MACPHERSON , Ben ASHBAUGH , Murali RAMADOSS , Vikranth VEMULAPALLI , William SADLER , Jonathan PEARCE , Sungye KIM
CPC classification number: G06F15/8069 , G06F9/30163 , G06F9/3877 , G06T15/005 , G06F9/3836
Abstract: Methods and apparatus relating to scalar core integration in a graphics processor. In an example, an apparatus comprises a processor to receive a set of workload instructions for a graphics workload from a host complex, determine a first subset of operations in the set of operations that is suitable for execution by a scalar processor complex of the graphics processing device and a second subset of operations in the set of operations that is suitable for execution by a vector processor complex of the graphics processing device, assign the first subset of operations to the scalar processor complex for execution to generate a first set of outputs, assign the second subset of operations to the vector processor complex for execution to generate a second set of outputs. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20230315462A1
公开(公告)日：2023-10-05
申请号：US17712127
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
CPC classification number: G06F9/3017 , G06F9/223 , G06F9/3009
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
-
公开(公告)号：US20230315461A1
公开(公告)日：2023-10-05
申请号：US17712130
申请日：2022-04-02
Applicant: Intel Corporation
Inventor： David B. SHEFFIELD , Erich BOLEYN , Jonathan PEARCE , Sofia PEDIADITAKI , Jeffrey COOK , Shreesha SRINATH , Ching-Kai LIANG , Tyler SONDAG
IPC: G06F9/30
CPC classification number: G06F9/3016 , G06F9/3009
Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
-
-
-
-
-
-
-
-
-
Search Results
11
records
(took 0.017 seconds)
