公开(公告)号：US20230315455A1

公开(公告)日：2023-10-05

申请号：US17712118

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： David B. SHEFFIELD ,  Erich BOLEYN ,  Jonathan PEARCE ,  Sofia PEDIADITAKI ,  Jeffrey COOK ,  Shreesha SRINATH ,  Ching-Kai LIANG ,  Tyler SONDAG

IPC: G06F9/30

CPC classification number: G06F9/3009 ,  G06F9/30105 ,  G06F9/30043 ,  G06F9/30047

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

公开(公告)号：US20230315458A1

公开(公告)日：2023-10-05

申请号：US17712120

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： Shreesha SRINATH ,  Jonathan PEARCE ,  David B. SHEFFIELD ,  Ching-Kai LIANG ,  Jeffrey COOK

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30065 ,  G06F9/3009

Abstract: Techniques for using soft-barrier hints are described. An example includes a synchronous microthreading (SyMT) co-processor coupled to a logical processor to execute a plurality of microthreads, with each microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode, wherein the SyMT co-processor is further to support a soft-barrier hint instruction in code which when processed by a microthread is to pause execution of the microthread to be resumed based at least in part on a data structure having at least one entry, the entry to include an instruction pointer of the soft-barrier hint instruction and a count of microthreads that have encountered the soft-barrier hint instruction at the instruction pointer.

公开(公告)号：US20230315462A1

公开(公告)日：2023-10-05

申请号：US17712127

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： David B. SHEFFIELD ,  Erich BOLEYN ,  Jonathan PEARCE ,  Sofia PEDIADITAKI ,  Jeffrey COOK ,  Shreesha SRINATH ,  Ching-Kai LIANG ,  Tyler SONDAG

IPC: G06F9/30 ,  G06F9/22

CPC classification number: G06F9/3017 ,  G06F9/223 ,  G06F9/3009

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

公开(公告)号：US20230315461A1

公开(公告)日：2023-10-05

申请号：US17712130

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： David B. SHEFFIELD ,  Erich BOLEYN ,  Jonathan PEARCE ,  Sofia PEDIADITAKI ,  Jeffrey COOK ,  Shreesha SRINATH ,  Ching-Kai LIANG ,  Tyler SONDAG

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/3009

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

公开(公告)号：US20230315444A1

公开(公告)日：2023-10-05

申请号：US17712124

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： David B. SHEFFIELD ,  Erich BOLEYN ,  Jonathan PEARCE ,  Sofia PEDIADITAKI ,  Jeffrey COOK ,  Shreesha SRINATH ,  Ching-Kai LIANG ,  Tyler SONDAG

IPC: G06F9/22 ,  G06F9/30

CPC classification number: G06F9/223 ,  G06F9/3017 ,  G06F9/30101

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

公开(公告)号：US20250123881A1

公开(公告)日：2025-04-17

申请号：US18927065

申请日：2024-10-25

Applicant: Intel Corporation

Inventor： Rajesh M. SANKARAN ,  Gilbert NEIGER ,  Narayan RANGANATHAN ,  Stephen R. VAN DOREN ,  Joseph NUZMAN ,  Niall D. MCDONNELL ,  Michael A. O'HANLON ,  Lokpraveen B. MOSUR ,  Tracy Garrett DRYSDALE ,  Eriko NURVITADHI ,  Asit K. MISHRA ,  Ganesh VENKATESH ,  Deborah T. MARR ,  Nicholas P. CARTER ,  Jonathan D. PEARCE ,  Edward T. GROCHOWSKI ,  Richard J. GRECO ,  Robert VALENTINE ,  Jesus CORBAL ,  Thomas D. FLETCHER ,  Dennis R. BRADFORD ,  Dwight P. MANLEY ,  Mark J. CHARNEY ,  Jeffry J. COOK ,  Paul CAPRIOLI ,  Koichi YAMADA ,  Kent D. GLOSSOP ,  David B. SHEFFIELD

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US20230315572A1

公开(公告)日：2023-10-05

申请号：US17712121

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： David B. SHEFFIELD ,  Erich BOLEYN ,  Jonathan PEARCE ,  Sofia PEDIADITAKI ,  Jeffrey COOK ,  Shreesha SRINATH ,  Ching-Kai LIANG ,  Tyler SONDAG

IPC: G06F11/14 ,  G06F9/38 ,  G06F9/22 ,  G06F9/30 ,  G06F15/78

CPC classification number: G06F11/1405 ,  G06F9/3861 ,  G06F15/7889 ,  G06F9/3009 ,  G06F9/226

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

公开(公告)号：US20230315459A1

公开(公告)日：2023-10-05

申请号：US17712122

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： David B. SHEFFIELD ,  Erich BOLEYN ,  Jonathan PEARCE ,  Sofia PEDIADITAKI ,  Jeffrey COOK ,  Shreesha SRINATH ,  Ching-Kai LIANG ,  Tyler SONDAG

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/3009 ,  G06F9/3013

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

公开(公告)号：US20230315445A1

公开(公告)日：2023-10-05

申请号：US17712126

申请日：2022-04-02

Applicant: Intel Corporation

Inventor： David B. SHEFFIELD ,  Erich BOLEYN ,  Jonathan PEARCE ,  Sofia PEDIADITAKI ,  Jeffrey COOK ,  Shreesha SRINATH ,  Ching-Kai LIANG ,  Tyler SONDAG

IPC: G06F9/22 ,  G06F9/30

CPC classification number: G06F9/223 ,  G06F9/30101 ,  G06F9/3009

Abstract: Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.

公开(公告)号：US20240211583A1

公开(公告)日：2024-06-27

申请号：US18087776

申请日：2022-12-22

Applicant: Intel Corporation

Inventor： Alexander EYDELBERG ,  Salessawi Ferede YITBAREK ,  David B. SHEFFIELD ,  Xiang ZOU

IPC: G06F21/45

CPC classification number: G06F21/45

Abstract: An apparatus and method for improved processor security and authenticated code execution. For example, one embodiment of a processor comprises: a secure memory to store an authenticated code module (ACM); and security hardware logic to select a mode of operation for processing the ACM based on a microarchitecture of the processor, the security hardware logic to validate the ACM and parse a header of the ACM to determine an entry point for processing the ACM in accordance with the microarchitecture.