发明公开
- 专利标题: BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME
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申请号: US18446028申请日: 2023-08-08
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公开(公告)号: US20230387051A1公开(公告)日: 2023-11-30
- 发明人: Chen-Yu Tsai , Ku-Feng Yang , Wen-Chih Chiou
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 分案原申请号: US17186742 2021.02.26
- 主分类号: H01L23/00
- IPC分类号: H01L23/00
摘要:
A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.
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