公开(公告)号：US20240371804A1

公开(公告)日：2024-11-07

申请号：US18775442

申请日：2024-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Tsai ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC: H01L23/00

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

公开(公告)号：US12087732B2

公开(公告)日：2024-09-10

申请号：US18338013

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Ku-Feng Yang ,  Yung-Chi Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/683 ,  H01L21/82 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/6836 ,  H01L21/82 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582

Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

公开(公告)号：US11990430B2

公开(公告)日：2024-05-21

申请号：US17186742

申请日：2021-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Tsai ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/03013 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0355 ,  H01L2224/03612 ,  H01L2224/03622 ,  H01L2224/0381 ,  H01L2224/05083 ,  H01L2224/05084 ,  H01L2224/05546 ,  H01L2224/05564 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/2781 ,  H01L2224/27831 ,  H01L2224/29006 ,  H01L2224/29027 ,  H01L2224/29028 ,  H01L2224/32145 ,  H01L2224/32225

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

公开(公告)号：US20230387051A1

公开(公告)日：2023-11-30

申请号：US18446028

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Yu Tsai ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC: H01L23/00

CPC classification number: H01L24/03 ,  H01L24/29 ,  H01L24/27 ,  H01L24/05 ,  H01L2224/27831 ,  H01L2224/03622 ,  H01L2224/03013 ,  H01L2224/0381 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03612 ,  H01L2224/0355 ,  H01L2224/05084 ,  H01L2224/05083 ,  H01L2224/05546 ,  H01L2224/05564 ,  H01L2224/29006 ,  H01L2224/29028 ,  H01L2224/29027 ,  H01L24/08 ,  H01L24/32 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/2781

Abstract: A method includes forming a conductive pad over an interconnect structure of a wafer, forming a capping layer over the conductive pad, forming a dielectric layer covering the capping layer, and etching the dielectric layer to form an opening in the dielectric layer. The capping layer is exposed to the opening. A wet-cleaning process is then performed on the wafer. During the wet-cleaning process, a top surface of the capping layer is exposed to a chemical solution used for performing the wet-cleaning process. The method further includes depositing a conductive diffusion barrier extending into the opening, and depositing a conductive material over the conductive diffusion barrier.

公开(公告)号：US20220344301A1

公开(公告)日：2022-10-27

申请号：US17457704

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Chih Chiou ,  Ku-Feng Yang ,  Ming-Tsu Chung

IPC: H01L23/00

Abstract: A method includes putting a first package component into contact with a second package component. The first package component comprises a first dielectric layer including a first dielectric material, and the first dielectric material is a silicon-oxide-based dielectric material. The second package component includes a second dielectric layer including a second dielectric material different from the first dielectric material. The second dielectric material comprises silicon and an element selected from the group consisting of carbon, nitrogen, and combinations thereof. An annealing process is performed to bond the first dielectric layer to the second dielectric layer.

公开(公告)号：US20170062392A1

公开(公告)日：2017-03-02

申请号：US14840053

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuang-Wei Cheng ,  Yi-Hsiu Chen ,  Ku-Feng Yang ,  Wen-Chih Chiou

IPC: H01L25/07 ,  H01L25/00 ,  H01L23/538

CPC classification number: H01L25/50 ,  H01L21/48 ,  H01L23/522 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2224/11 ,  H01L2225/06541 ,  H01L2225/06544

Abstract: Three dimensional integrated circuit structures and manufacturing methods of the same are disclosed. The three dimensional integrated circuit structure includes a first chip and a second chip. The first chip is bonded to the second chip at a bonding interface. A through via of the first chip and a bonding pad of the second chip are electrically connected, and a diffusion barrier layer of the through via contacts the bonding pad at the bonding interface.

Abstract translation: 公开了三维集成电路结构及其制造方法。 三维集成电路结构包括第一芯片和第二芯片。 第一芯片在接合界面处接合到第二芯片。 第一芯片的通孔和第二芯片的焊盘电连接，并且通孔的扩散阻挡层在接合界面处接触焊盘。

公开(公告)号：US20250132150A1

公开(公告)日：2025-04-24

申请号：US18582070

申请日：2024-02-20

Applicant: Taiwan Semiconductor manufacturing Co., Ltd.

Inventor： Che Chi Shih ,  Chun-Yu Liu ,  James June Fan Hsu ,  Ku-Feng Yang ,  Szuya Liao

IPC: H01L21/02 ,  H01L21/324 ,  H01L29/66

Abstract: A method includes forming a first de-bond structure over a first substrate, where forming the first de-bond structure includes depositing a first de-bond layer over the first substrate, depositing a first silicon layer over the first de-bond layer, depositing a second de-bond layer over the first silicon layer, and depositing a second silicon layer over the second de-bond layer, epitaxially growing a first multi-layer stack over the first de-bond structure, bonding the first multi-layer stack to a second multi-layer stack, and performing a first laser annealing process to ablate the first silicon layer and portions of the first de-bond layer and the second de-bond layer in order to de-bond the first substrate from the first multi-layer stack.

公开(公告)号：US20240363411A1

公开(公告)日：2024-10-31

申请号：US18768673

申请日：2024-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/481 ,  H01L23/53295

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

公开(公告)号：US12074064B2

公开(公告)日：2024-08-27

申请号：US17814775

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Ku-Feng Yang ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/481 ,  H01L23/53295

Abstract: A method includes forming a plurality of dielectric layers over a semiconductor substrate, etching the plurality of dielectric layers and the semiconductor substrate to form an opening, depositing a first liner extending into the opening, and depositing a second liner over the first liner. The second liner extends into the opening. The method further includes filling a conductive material into the opening to form a through-via, and forming conductive features on opposing sides of the semiconductor substrate. The conductive features are electrically interconnected through the through-via.

公开(公告)号：US20210125900A1

公开(公告)日：2021-04-29

申请号：US17142190

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Ku-Feng Yang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522

Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.