发明公开
- 专利标题: WAFER PLACEMENT TABLE
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申请号: US18298404申请日: 2023-04-11
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公开(公告)号: US20230402306A1公开(公告)日: 2023-12-14
- 发明人: Reo WATANABE , Daisuke TSUNEKAWA , Kanto WATANABE
- 申请人: NGK INSULATORS, LTD.
- 申请人地址: JP Nagoya-City
- 专利权人: NGK INSULATORS, LTD.
- 当前专利权人: NGK INSULATORS, LTD.
- 当前专利权人地址: JP Nagoya-City
- 优先权: JP 22094256 2022.06.10
- 主分类号: H01L21/677
- IPC分类号: H01L21/677 ; H01L21/683
摘要:
A wafer placement table includes: a ceramic substrate having a wafer placement surface and incorporating an electrode; a conductive embedded member electrically connected to the electrode; a conductive terminal with a female thread, the conductive terminal being electrically connected to the conductive embedded member, having a projection projecting from a surface, on an opposite side to the wafer placement surface, of the ceramic substrate, having the female thread at an end face of the projection; a conductive adapter that is mounted on the end face of the projection of the conductive terminal with the female thread, has a communication hole that communicates with the female thread, and is non-rotatable relative to the conductive terminal with the female thread; and a conductive connection member with a male thread, the conductive connection member having the male thread screwed into the female thread through the communication hole, and being integrated with the adapter.
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