Dynamic tile sequencing in graphics processing is described. An example of an apparatus includes one or more processors including a graphics processor, the one or more processor including a plurality of portions and tile sequencing circuitry; and a memory to store data for graphics processing, including data for a render target and data for a hashing table, the render target including a plurality of tiles, and the hashing table to map the tiles of the render target to the plurality of portions of the one or more processors, wherein the tile sequencing circuitry includes a first mode for tile sequencing, wherein tile sequencing in the first mode includes a set granularity for the hashing table; and a second mode for tiling sequencing, wherein tile sequencing in the second mode includes a configurable granularity for the hashing table.