公开(公告)号：US12190406B2

公开(公告)日：2025-01-07

申请号：US17359528

申请日：2021-06-26

Applicant: Intel Corporation

Inventor： Raghavendra Kamath Miyar ,  Rajalakshmi Athimoolam ,  Subramaniam Maiyuran ,  Jorge F. Garcia Pabon ,  Rajarshi Bajpayee ,  Krishan Malik

IPC: G06T1/60 ,  G06T1/20

Abstract: Examples described herein relate to an apparatus comprising: at least one memory and at least one processor. In some example, the at least one processor is to: represent at least one vertex in a set of vertices of a first polygon using a first index; store the first index into the at least one memory; and indicate whether the first index is to be de-referenced based on a comparison between the first index and at least one other index, wherein: a first memory pointer is associated with the at least one vertex in the set of vertices of the first polygon and the first index comprises a number of bits that is less than a number of bits associated with the first memory pointer. In some examples, the number of bits of the first index is based on a size of a vertex window and wherein the vertex window comprises multiple vertices associated with one or more draw calls. In some examples, the number of bits of the first index is N and 2N is a size of a vertex window and wherein the vertex window comprises 2N vertices associated with one or more draw calls.

公开(公告)号：US20220198735A1

公开(公告)日：2022-06-23

申请号：US17128708

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge F. Garcia Pabon ,  Raghavendra Kamath Miyar ,  Sudheendra Srivathsa ,  Krishan Malik ,  Narsim Krishna ,  Rajalakshmi Athimoolam ,  Amit Mishra

IPC: G06T15/00 ,  G06T11/40 ,  G06T1/20 ,  G06T1/60

Abstract: An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises tiling hardware to perform tile based rendering of objects, including receiving a workload comprising a plurality of objects, performing batch formation to generate one or more batches of the plurality of objects, performing super tile fill sequencing for to determine one or more super tiles that are intersected by objects in each batch and compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects, wherein each super tile comprises a plurality of tiles.

公开(公告)号：US20230095535A1

公开(公告)日：2023-03-30

申请号：US17485017

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge F. Garcia Pabon ,  Raghavendra Kamath Miyar ,  Sudheendra Srivathsa ,  Krishan Malik

IPC: G06T15/00 ,  G06T1/20 ,  G06T1/60

Abstract: Dynamic tile sequencing in graphics processing is described. An example of an apparatus includes one or more processors including a graphics processor, the one or more processor including a plurality of portions and tile sequencing circuitry; and a memory to store data for graphics processing, including data for a render target and data for a hashing table, the render target including a plurality of tiles, and the hashing table to map the tiles of the render target to the plurality of portions of the one or more processors, wherein the tile sequencing circuitry includes a first mode for tile sequencing, wherein tile sequencing in the first mode includes a set granularity for the hashing table; and a second mode for tiling sequencing, wherein tile sequencing in the second mode includes a configurable granularity for the hashing table.

公开(公告)号：US20220383569A1

公开(公告)日：2022-12-01

申请号：US17331913

申请日：2021-05-27

Applicant: Intel Corporation

Inventor： Jorge Garcia Pabon ,  Subramaniam Maiyuran ,  Raghavendra Kamath Miyar ,  Vamsee Vardhan Chivukula ,  Krishan Malik ,  Abhishek Varshney

IPC: G06T11/40 ,  G06T1/20 ,  G06T15/00

Abstract: Methods, systems and apparatuses may provide for technology that selects a location of a pixel block based on a location of a graphics polygon, wherein the pixel block contains the graphics polygon. The technology may also convert the graphics polygon into a pixel-based representation within the pixel block during a single transaction.