Invention Publication
- Patent Title: Gate Isolation Wall for Semiconductor Device
-
Application No.: US18188306Application Date: 2023-03-22
-
Publication No.: US20240014265A1Publication Date: 2024-01-11
- Inventor: Lung-Kun CHU , Jia-Ni YU , Chun-Fu LU , Chung-Wei HSU , Mao-Lin HUANG , Kuo-Cheng CHIANG , Chih-Hao WANG
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/786 ; H01L29/775 ; H01L29/66 ; H01L29/423 ; H01L27/092 ; H01L21/8238

Abstract:
The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.
Information query
IPC分类: