Gate Isolation Wall for Semiconductor Device
Abstract:
The present disclosure describes a semiconductor device having an isolation structure. The semiconductor structure includes a set of nanostructures on a substrate, a gate dielectric layer wrapped around the set of nanostructures, a work function metal layer on the gate dielectric layer and around the set of nanostructures, and the isolation structure adjacent to the set of nanostructures and in contact with the work function metal layer. A portion of the work function metal layer is on a top surface of the isolation structure.
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