Invention Publication
- Patent Title: Integrated Circuit Package and Method of Forming the Same
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Application No.: US17817738Application Date: 2022-08-05
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Publication No.: US20240047417A1Publication Date: 2024-02-08
- Inventor: Der-Chyang Yeh , Sung-Feng Yeh , Jian-Wei Hong
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L25/065
- IPC: H01L25/065 ; H01L23/00 ; H01L25/00

Abstract:
A method includes attaching a first die and a second die to a first wafer, the first wafer comprising: a first carrier substrate; and a first interconnect structure comprising first dielectric layers and first conductive features embedded in the first dielectric layers; attaching a third die to the first die and a fourth die to the second die; attaching a second wafer to the third die and the fourth die, the second wafer comprising: a second carrier substrate; and a second interconnect structure comprising second dielectric layers and second conductive features embedded in the second dielectric layers; removing the first carrier substrate; patterning the first dielectric layers to expose conductive features of the first die and the second die; and forming external connectors through the first dielectric layers, the external connectors being electrically connected to corresponding ones of the conductive features of the first die and the second die.
Information query
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