公开(公告)号：US20240387452A1

公开(公告)日：2024-11-21

申请号：US18785335

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/306 ,  H01L21/768 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US20240379614A1

公开(公告)日：2024-11-14

申请号：US18782253

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

IPC: H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065

Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

公开(公告)号：US12125819B2

公开(公告)日：2024-10-22

申请号：US17883999

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/304 ,  H01L21/306

CPC classification number: H01L24/94 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/92 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L21/304 ,  H01L21/30625 ,  H01L21/76898 ,  H01L24/06 ,  H01L24/33 ,  H01L2224/03845 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/27831 ,  H01L2224/2784 ,  H01L2224/27845 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29016 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/83203 ,  H01L2224/83896 ,  H01L2224/9211 ,  H01L2225/06544

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US20240266297A1

公开(公告)日：2024-08-08

申请号：US18602718

申请日：2024-03-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Hsien-Wei Chen

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/80 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A package includes a redistribution structure, a die package on a first side of the redistribution structure including a first die connected to a second die by metal-to-metal bonding and dielectric-to-dielectric bonding, a dielectric material over the first die and the second die and surrounding the first die, and a first through via extending through the dielectric material and connected to the first die and a first via of the redistribution structure, a semiconductor device on the first side of the redistribution structure includes a conductive connector, wherein a second via of the redistribution structure contacts the conductive connector of the semiconductor device, a first molding material on the redistribution structure and surrounding the die package and the semiconductor device, and a package through via extending through the first molding material to contact a third via of the redistribution structure.

公开(公告)号：US20240222339A1

公开(公告)日：2024-07-04

申请号：US18152665

申请日：2023-01-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L24/95 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L24/13 ,  H01L2224/05647 ,  H01L2224/08237 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/95001 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: In an embodiment, a device includes a first integrated circuit die, wherein the first integrated circuit die includes a substrate formed of a semiconductor material and a conductive via penetrating through the substrate; a second integrated circuit die disposed laterally adjacent to the first integrated circuit die; a first gap-filling layer disposed between the first integrated circuit die and the second integrated circuit die, wherein the first gap-filling layer is formed of a material selected from silicon, silicon carbide, silicon oxynitride, silicon nitride, the semiconductor material of the substrate, or a combination thereof; and a third integrated circuit die attached to the first integrated circuit die in a face-to-back manner.

公开(公告)号：US20230378012A1

公开(公告)日：2023-11-23

申请号：US17896840

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Min-Chien Hsiao ,  Chun-Chiang Kuo ,  Tsung-Shu Lin

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/3192 ,  H01L21/568 ,  H01L23/3185 ,  H01L25/0655 ,  H01L25/0652 ,  H01L25/50 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/20 ,  H01L25/105 ,  H01L24/19 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L24/06 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/80201 ,  H01L2224/80896 ,  H01L2224/211 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1041 ,  H01L2224/19

Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die; a gap-fill dielectric between a first sidewall of the first integrated circuit die and a second sidewall of the second integrated circuit die; a protective cap overlapping the gap-fill dielectric, the first sidewall of the first integrated circuit die, and the second sidewall of the second integrated circuit die; and an isolation layer around the protective cap, the isolation layer disposed on the first integrated circuit die, and the second integrated circuit die.

公开(公告)号：US11664349B2

公开(公告)日：2023-05-30

申请号：US17099395

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L25/065 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/56 ,  H01L21/66

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/80 ,  H01L24/82 ,  H01L24/94 ,  H01L24/96 ,  H01L21/568 ,  H01L22/32 ,  H01L23/3135 ,  H01L24/08 ,  H01L2224/04105 ,  H01L2224/05571 ,  H01L2224/06517 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/08225 ,  H01L2224/09517 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80948 ,  H01L2224/80986 ,  H01L2224/821 ,  H01L2224/82031 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/94 ,  H01L2224/80 ,  H01L2224/821 ,  H05K3/467 ,  H01L2224/9222 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2224/80896 ,  H01L2924/00012

Abstract: A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip.

公开(公告)号：US20220384314A1

公开(公告)日：2022-12-01

申请号：US17883999

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chao-Wen Shih ,  Sung-Feng Yeh

IPC: H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

Abstract: A package structure and method of manufacturing is provided, whereby a bonding dielectric material layer is provided at a back side of a wafer, a bonding dielectric material layer is provided at a front side of an adjoining wafer, and wherein the bonding dielectric material layers are fusion bonded to each other.

公开(公告)号：US11495559B2

公开(公告)日：2022-11-08

申请号：US16859914

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L29/40 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: One of integrated circuits includes a substrate, a through via, a conductive pad and at least one via. The through via is disposed in the substrate. The conductive pad is disposed over and electrically connected to the through via, and the conductive pad includes at least one dielectric pattern therein. The via is disposed between and electrically connected to the through via and the conductive pad.

公开(公告)号：US11417629B2

公开(公告)日：2022-08-16

申请号：US16787031

申请日：2020-02-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Tzuan-Horng Liu ,  Chao-Wen Shih

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L25/00

Abstract: A stacking structure including a first die, a second die stacked on the first die, and a third die and a fourth die disposed on the second die. The first die has a first metallization structure, and the first metallization structure includes first through die vias. The second die has a second metallization structure, and second metallization structure includes second through die vias. The first through die vias are bonded with the second through die vias, and sizes of the first through die vias are different from sizes of the second through die vias. The third and fourth dies are disposed side-by-side and are bonded with the second through die vias.