公开(公告)号：US11227812B2

公开(公告)日：2022-01-18

申请号：US16745355

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/544 ,  H01L25/00 ,  H01L21/768 ,  H01L21/463 ,  H01L25/065 ,  H01L21/56

Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

公开(公告)号：US20240079364A1

公开(公告)日：2024-03-07

申请号：US18151856

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hao Hsu ,  Jian-Wei Hong ,  Kuo-Chiang Ting ,  Sung-Feng Yeh

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/24 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/19 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/24105 ,  H01L2224/24146 ,  H01L2224/244 ,  H01L2224/80201 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/9212 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0504 ,  H01L2924/0544 ,  H01L2924/0549 ,  H01L2924/05494 ,  H01L2924/07025

Abstract: Die structures and methods of forming the same are described. In an embodiment, a device includes: a lower integrated circuit die; a first upper integrated circuit die face-to-face bonded to the lower integrated circuit die, the first upper integrated circuit die including a first semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first upper integrated circuit die, a top surface of the gap-fill dielectric being substantially coplanar with a top surface of the first semiconductor substrate and with a top surface of the first through-substrate via; and an interconnect structure including a first dielectric layer and first conductive vias, the first dielectric layer disposed on the top surface of the gap-fill dielectric and the top surface of the first semiconductor substrate, the first conductive vias extending through the first dielectric layer to contact the top surface of the first through-substrate via.

公开(公告)号：US20210066168A1

公开(公告)日：2021-03-04

申请号：US16745355

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/544 ,  H01L21/56 ,  H01L21/768 ,  H01L21/463 ,  H01L25/065 ,  H01L25/00

Abstract: A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, a first through insulating via (TIV), and a second TIV. The semiconductor carrier has a contact via embedded therein. The contact via is electrically grounded. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The first TIV is aside the first die. The first TIV penetrates through the first encapsulant and is electrically connected to the contact via. The second TIV is aside the second die. The second TIV penetrates through the second encapsulant and is electrically connected to the contact via and the first TIV.

公开(公告)号：US20230335534A1

公开(公告)日：2023-10-19

申请号：US17865969

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L25/50 ,  H01L24/97

Abstract: In an embodiment, a device includes: a first integrated circuit die; a second integrated circuit die bonded to the first integrated circuit die in a face-to-back manner; a dummy semiconductor feature adjacent the second integrated circuit die and bonded to the first integrated circuit die; a support substrate attached to the dummy semiconductor feature and the second integrated circuit die; and a passivation layer extending along a top surface of the support substrate, an outer sidewall of the dummy semiconductor feature, an outer sidewall of the first integrated circuit die, and a top surface of the first integrated circuit die.

公开(公告)号：US20250069985A1

公开(公告)日：2025-02-27

申请号：US18543819

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Jian-Wei Hong

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A method includes bonding a bottom die to a carrier, and bonding a top die to the bottom die. The top die includes a semiconductor substrate, and the semiconductor substrate has a first thermal conductivity. The method further includes encapsulating the top die in a gap-fill region, bonding a supporting substrate to the top die and the gap-fill region to form a reconstructed wafer, wherein the supporting substrate has a second thermal conductivity higher than the first thermal conductivity, de-bonding the reconstructed wafer from the carrier, and forming electrical connectors on the bottom die.

公开(公告)号：US20240047417A1

公开(公告)日：2024-02-08

申请号：US17817738

申请日：2022-08-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method includes attaching a first die and a second die to a first wafer, the first wafer comprising: a first carrier substrate; and a first interconnect structure comprising first dielectric layers and first conductive features embedded in the first dielectric layers; attaching a third die to the first die and a fourth die to the second die; attaching a second wafer to the third die and the fourth die, the second wafer comprising: a second carrier substrate; and a second interconnect structure comprising second dielectric layers and second conductive features embedded in the second dielectric layers; removing the first carrier substrate; patterning the first dielectric layers to expose conductive features of the first die and the second die; and forming external connectors through the first dielectric layers, the external connectors being electrically connected to corresponding ones of the conductive features of the first die and the second die.

公开(公告)号：US11373981B2

公开(公告)日：2022-06-28

申请号：US16786969

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/60 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00

Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.

公开(公告)号：US20210066248A1

公开(公告)日：2021-03-04

申请号：US16786969

申请日：2020-02-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Sung-Feng Yeh ,  Jian-Wei Hong

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/60 ,  H01L21/683 ,  H01L25/00

Abstract: A package includes a first die, a second die, a first encapsulant, first through insulating vias (TIV), a second encapsulant, and second TIVs. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The first TIVs are aside the first die. The first TIVs penetrate through the first encapsulant and are electrically floating. The second encapsulant laterally encapsulates the second die. The second TIVs are aside the second die. The second TIVs penetrate through the second encapsulant and are electrically floating. The second TIVs are substantially aligned with the first TIVs.