Invention Publication
- Patent Title: SCALABLE HIGH SPEED HIGH BANDWIDTH IO SIGNALING PACKAGE ARCHITECTURE AND METHOD OF MAKING
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Application No.: US18516579Application Date: 2023-11-21
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Publication No.: US20240088047A1Publication Date: 2024-03-14
- Inventor: Sanka Ganesan , Robert L. Sankman , Arghya Sain , Sri Chaitra Jyotsna Chavali , Lijiang Wang , Cemil Geyik
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- The original application number of the division: US16521435 2019.07.24
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/498

Abstract:
Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.
Information query
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