公开(公告)号：US20240332193A1

公开(公告)日：2024-10-03

申请号：US18192804

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Sujit Sharan

IPC: H01L23/538

CPC classification number: H01L23/5381 ,  H01L23/5386

Abstract: In one embodiment, an interconnect bridge circuitry includes a first set of bridge-to-die electrical connectors in a first region of the circuitry, a second set of bridge-to-die electrical connectors in a second region of the circuitry, and an interconnection between a bridge-to-die connector of the first set and a bridge-to-die connector of the second set. The interconnection is in a third region of the circuitry between the first region and the second region, and includes a first trace connected to the bridge-to-die electrical connector of the first set, a second trace connected to the bridge-to-die electrical connector of the second set, the second trace parallel with the first trace, and a third trace connected between the first trace and the second trace.

公开(公告)号：US12057413B2

公开(公告)日：2024-08-06

申请号：US16393047

申请日：2019-04-24

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Arghya Sain ,  Xiaohong Jiang ,  Sujit Sharan ,  Kemal Aygun

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2924/30111

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

公开(公告)号：US11114394B2

公开(公告)日：2021-09-07

申请号：US16536997

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Sujit Sharan ,  Robert L. Sankman

IPC: H01L23/66 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01P3/08 ,  H01P11/00 ,  H01L23/14

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.

公开(公告)号：US20210043588A1

公开(公告)日：2021-02-11

申请号：US16536997

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Jianyong Xie ,  Sujit Sharan ,  Robert L. Sankman

IPC: H01L23/66 ,  H01L23/14 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01P3/08 ,  H01P11/00

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes an article having a substrate, a semiconductor die thereon, a routing carrier attached to the substrate, and a transmission pathway electrically connected to the semiconductor die and the substrate, wherein the transmission pathway runs through the routing carrier. In selected examples, the article is made by manufacturing a substrate, attaching a semiconductor die to the substrate, fabricating a routing carrier comprising a transmission pathway, and integrating the routing carrier into the substrate.

公开(公告)号：US11869842B2

公开(公告)日：2024-01-09

申请号：US16521435

申请日：2019-07-24

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Robert L. Sankman ,  Arghya Sain ,  Sri Chaitra Jyotsna Chavali ,  Lijiang Wang ,  Cemil Geyik

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.

公开(公告)号：US20240006323A1

公开(公告)日：2024-01-04

申请号：US17853018

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Lijiang Wang ,  Naren Sreenivas Viswanathan ,  Sujit Sharan ,  Jiwei Sun

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/5386 ,  H01L23/5383 ,  H01L25/0655

Abstract: An electronic device may include an interconnect bridge. The interconnect bridge may include a first electrical routing trace having a first routing length and a corresponding first transit time for a first electrical signal to transmit across the first routing length. The first electrical routing trace may transmit the first electrical signal along a major plane of the interconnect bridge between a first interconnect and a second interconnect. The interconnect bridge may include a routing trace deviation in communication with the first electrical routing trace. The routing trace deviation is outside a direct route between the first interconnect and the second interconnect. The routing trace deviation may alter one or more of capacitance or resistance of the first electrical routing trace and correspondingly alter the first routing time.

公开(公告)号：US20240088047A1

公开(公告)日：2024-03-14

申请号：US18516579

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Robert L. Sankman ,  Arghya Sain ,  Sri Chaitra Jyotsna Chavali ,  Lijiang Wang ,  Cemil Geyik

IPC: H01L23/538 ,  H01L23/498

CPC classification number: H01L23/5381 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, wherein the package substrate comprises a first routing architecture. In an embodiment, the electronic package further comprises a first die on the package substrate, a second die on the package substrate, wherein the first die is electrically coupled to the second die by a bridge embedded in the package substrate, and a routing patch on the package substrate. In an embodiment, the routing patch is electrically coupled to the second die, and wherein the routing patch comprises a second routing architecture that is different than the first routing architecture.