Invention Publication
- Patent Title: SPLIT VIA STRUCTURES COUPLED TO CONDUCTIVE LINES FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
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Application No.: US17956775Application Date: 2022-09-29
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Publication No.: US20240113019A1Publication Date: 2024-04-04
- Inventor: Leonard P. GULER , Mohit K. HARAN , Nikhil MEHTA , Charles H. WALLACE , Tahir GHANI , Sukru YEMENICIOGLU
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/522

Abstract:
Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive lines in a first inter-layer dielectric (ILD) layer, the plurality of conductive lines on a same level and along a same direction. A second ILD layer is over the plurality of conductive lines and over the first ILD layer. A first conductive via is in a first opening in the second ILD layer, the first conductive via in contact with a first one of the plurality of conductive lines, the first conductive via having a straight edge. A second conductive via is in a second opening in the second ILD layer, the second conductive via in contact with a second one of the plurality of conductive lines, the second one of the plurality of conductive lines laterally spaced apart from the first one of the plurality of conductive lines, and the second conductive via having a straight edge, the straight edge of the second conductive via facing the straight edge of the first conductive via.
Information query
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