Invention Publication
- Patent Title: SELF-ALIGNED PATTERNING OF PLATE LINES IN THREE-DIMENSIONAL FERROELECTRIC CAPACITORS
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Application No.: US17958202Application Date: 2022-09-30
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Publication No.: US20240114693A1Publication Date: 2024-04-04
- Inventor: Christopher M. Neumann , Brian Doyle , Nazila Haratipour , Shriram Shivaraman , Sou-Chi Chang , Uygar E. Avci , Eungnak Han , Manish Chandhok , Nafees Aminul Kabir , Gurpreet Singh
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L27/11514
- IPC: H01L27/11514 ; H01L23/522 ; H01L23/528 ; H01L27/11504
Abstract:
In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.
Information query
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