公开(公告)号：US11488978B2

公开(公告)日：2022-11-01

申请号：US16143933

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma ,  Elijah Karpov

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/11585 ,  H01L29/51 ,  H01L29/66 ,  H01L29/08

Abstract: A transistor is disclosed. The transistor includes a p-type region, an intrinsic region coupled to the p-type region, an n-type region coupled to the intrinsic region, and a gate electrode above the intrinsic region. The ferroelectric material is on a bottom, a first side and a second side of the gate electrode, and above the intrinsic region.

公开(公告)号：US11139401B2

公开(公告)日：2021-10-05

申请号：US16435359

申请日：2019-06-07

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Rami Hourani ,  Elijah Karpov ,  Prashant Majhi ,  Ravi Pillarisetty ,  Abhishek Sharma

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/11585 ,  H01L29/51 ,  H01L27/092 ,  H01L29/78

Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.

公开(公告)号：US20200235244A1

公开(公告)日：2020-07-23

申请号：US16650793

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Abhishek Sharma ,  Elijah Karpov ,  Ravi Pillarisetty ,  Prashant Majhi

IPC: H01L29/78 ,  H01L29/66

Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.

公开(公告)号：US20190304963A1

公开(公告)日：2019-10-03

申请号：US15940899

申请日：2018-03-29

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ilya Karpov ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma

IPC: H01L27/02 ,  H01L29/861

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises of the first material, wherein the second structure is between the first and third structures. Other embodiments are also disclosed and claimed.

公开(公告)号：US10201081B2

公开(公告)日：2019-02-05

申请号：US15676519

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H01L23/52 ,  H05K1/03 ,  D03D1/00 ,  D03D11/02 ,  D03D15/00 ,  H05K3/00 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K1/18 ,  H05K3/28

Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

公开(公告)号：US20240112714A1

公开(公告)日：2024-04-04

申请号：US17957591

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Christopher Neumann ,  Brian Doyle ,  Sou-Chi Chang ,  Bernal Granados Alpizar ,  Sarah Atanasov ,  Matthew Metz ,  Uygar Avci ,  Jack Kavalieros ,  Shriram Shivaraman

IPC: G11C11/22 ,  H01L27/11507 ,  H01L49/02

CPC classification number: G11C11/221 ,  H01L27/11507 ,  H01L28/55

Abstract: A memory device includes a group of ferroelectric capacitors with a shared plate that extends through the ferroelectric capacitors, has a greatest width between ferroelectric capacitors, and is coupled to an access transistor. The shared plate may be vertically between ferroelectric layers of the ferroelectric capacitors at the shared plate's greatest width. The memory device may include an integrated circuit die and be coupled to a power supply. Forming a group of ferroelectric capacitors includes forming an opening through an alternating stack of insulators and conductive plates, selectively forming ferroelectric material on the conductive plates rather than the insulators, and forming a shared plate in the opening over the ferroelectric material.

公开(公告)号：US11616057B2

公开(公告)日：2023-03-28

申请号：US16367144

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek Sharma ,  Brian Doyle ,  Ravi Pillarisetty ,  Willy Rachmady

IPC: H01L27/06 ,  H01L23/528 ,  H01L21/02 ,  H01L29/267

Abstract: IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

公开(公告)号：US11362140B2

公开(公告)日：2022-06-14

申请号：US16024199

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma ,  Elijah V. Karpov

IPC: H01L27/24 ,  G11C7/18 ,  G11C8/14 ,  H01L27/11597 ,  G11C13/00 ,  G11C11/22 ,  H01L45/00 ,  H01L29/78

Abstract: Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical.

公开(公告)号：US20200006433A1

公开(公告)日：2020-01-02

申请号：US16024199

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma ,  Elijah V. Karpov

IPC: H01L27/24 ,  G11C7/18 ,  G11C8/14 ,  H01L27/11597 ,  H01L29/78 ,  G11C13/00 ,  G11C11/22 ,  H01L45/00

Abstract: Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical.

公开(公告)号：US20200005861A1

公开(公告)日：2020-01-02

申请号：US16022547

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Brian Doyle ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster comprises a magnetic material layer. The booster may further comprise an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.