Invention Publication
- Patent Title: SEMICONDUCTOR WAFER CONFIGURED FOR SINGLE TOUCH-DOWN TESTING
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Application No.: US18221824Application Date: 2023-07-13
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Publication No.: US20240125846A1Publication Date: 2024-04-18
- Inventor: Toru Miwa , Takashi Murai , Hiroyuki Ogawa , Nisha Padattil Kuliyampattil
- Applicant: SanDisk Technologies LLC
- Applicant Address: US TX Addison
- Assignee: SanDisk Technologies LLC
- Current Assignee: SanDisk Technologies LLC
- Current Assignee Address: US TX Addison
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R1/073 ; H01L21/66 ; H01L23/522 ; H01L25/065
Abstract:
A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.
Public/Granted literature
- US12270853B2 Semiconductor wafer configured for single touch-down testing Public/Granted day:2025-04-08
Information query
