公开(公告)号：US20240128134A1

公开(公告)日：2024-04-18

申请号：US18221797

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Toru Miwa ,  Takashi Murai ,  Hiroyuki Ogawa

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L22/32

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

公开(公告)号：US20240125846A1

公开(公告)日：2024-04-18

申请号：US18221824

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Toru Miwa ,  Takashi Murai ,  Hiroyuki Ogawa ,  Nisha Padattil Kuliyampattil

IPC: G01R31/28 ,  G01R1/073 ,  H01L21/66 ,  H01L23/522 ,  H01L25/065

CPC classification number: G01R31/2884 ,  G01R1/07342 ,  H01L22/34 ,  H01L23/5228 ,  H01L25/0657 ,  H01L24/48 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2225/06562

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

公开(公告)号：US20210173734A1

公开(公告)日：2021-06-10

申请号：US16708383

申请日：2019-12-09

Applicant: SanDisk Technologies LLC

Inventor： Shih-Chung Lee ,  Takashi Murai ,  Ken Oowada

IPC: G06F11/07 ,  G06F11/14 ,  G06F11/30 ,  G06F12/02 ,  G06F13/16 ,  G11C29/12 ,  G11C16/34

Abstract: For a non-volatile memory die formed of multiple blocks of memory cells, the memory die has a multi-bit bad block flag for each block stored on the memory die, such as in a fuse ROM. For each block, the multi-bit flag indicates if the block has few defects and is of the highest reliability category, is too defective to be used, or is in of one of multiple recoverability categories. The multi-bit bad blocks values can be determined as part a test process on fresh devices, where the test of a block can be fail stop for critical category errors, but, for recoverable categories, the test continues and tracks the test results to determine a recoverability category for the block and write this onto the die as a bad block flag for each block. These recoverability categories can be incorporated into wear leveling operations.

公开(公告)号：US12270853B2

公开(公告)日：2025-04-08

申请号：US18221824

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Toru Miwa ,  Takashi Murai ,  Hiroyuki Ogawa ,  Nisha Padattil Kuliyampattil

IPC: G01R31/28 ,  G01R1/073 ,  H01L21/66 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

公开(公告)号：US20240128132A1

公开(公告)日：2024-04-18

申请号：US18221803

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Toru Miwa ,  Takashi Murai ,  Hiroyuki Ogawa ,  Nisha Padattil Kuliyampattil

IPC: H01L21/66 ,  G01R1/073 ,  H01L23/00

CPC classification number: H01L22/32 ,  G01R1/07342 ,  H01L24/05 ,  H01L24/06 ,  H01L25/0657

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.