- 专利标题: INTEGRATED CIRCUIT INCLUDING DIPOLE INCORPORATION FOR THRESHOLD VOLTAGE TUNING IN TRANSISTORS
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申请号: US18406025申请日: 2024-01-05
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公开(公告)号: US20240145470A1公开(公告)日: 2024-05-02
- 发明人: Lung-Kun CHU , Mao-Lin HUANG , Chung-Wei HSU , Jia-Ni YU , Kuo-Cheng CHIANG , Kuan-Lun CHENG , Chih-Hao WANG
- 申请人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址: TW Hsinchu
- 专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 主分类号: H01L27/088
- IPC分类号: H01L27/088 ; H01L21/8234 ; H01L29/06 ; H01L29/423 ; H01L29/786
摘要:
A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.
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