Invention Publication
- Patent Title: REDUCING CHARGE MIGRATION IN A MEMORY SYSTEM
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Application No.: US18516049Application Date: 2023-11-21
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Publication No.: US20240170052A1Publication Date: 2024-05-23
- Inventor: Amiya Banerjee , Kranthi Kumar Vaidyula , Jameer Mulani
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: G11C11/4096
- IPC: G11C11/4096 ; G11C11/408 ; G11C11/4093

Abstract:
Methods, systems, and devices for reducing charge migration in a memory system are described. The memory system may receive a command to program a first set of memory cells with first data. The memory system may generate a scrambling seed to scramble the first data. Before programming the scrambled data, the memory system may compare a first set of states in the scrambled data with a second set of states in second data to determine an aggregate difference between the sets of states. If the aggregate difference is less than a threshold, the memory system may program the first set of memory cells with the first data. If the aggregate difference is greater than a threshold, the memory system may generate a new scrambling seed to rescramble the first data and determine a new aggregate difference by comparing states of the rescrambled data to the states of the second data.
Information query
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