公开(公告)号：US20240345743A1

公开(公告)日：2024-10-17

申请号：US18603033

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Nitul Gohain ,  Amiya Banerjee ,  Rakeshkumar Dayabhai Vaghasiya

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive polling for higher density storage are described. A controller of a memory system may identify a temperature of the memory device and select one or more polling parameters that are associated with identifying a status of the memory device based on a temperature of a memory system. In some cases, the controller may perform a polling operation according to the one or more polling parameters based on selecting the one or more polling parameters.

公开(公告)号：US20240192890A1

公开(公告)日：2024-06-13

申请号：US18513310

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Amiya Banerjee ,  Nitul Gohain

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0625 ,  G06F3/0656 ,  G06F3/0683

Abstract: Methods, systems, and devices for data layout configurations for access operations are described. The memory system may write data to a first set of memory cells using a first write operation having a first type of layout for mapping the data to physical addresses of the memory system in response to receiving a write command. The first set of memory cells may be written to as single-level cells (SLCs), multi-level cells (MLCs), or triple-level cells (TLCs). The memory system may transfer the data to a second set of memory cells of the memory system using a second write operation having the first type of layout. The second set of memory cells may be written to as quad-level cells (QLCs). The memory system may read the data from the second set of memory cells using a read operation having a second type of layout different than the first type of layout.

公开(公告)号：US20240176491A1

公开(公告)日：2024-05-30

申请号：US18504992

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sridhar Prudviraj Gunda ,  Amiya Banerjee ,  Ritesh Tiwari ,  Shreesha Prabhu

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for an erase operation for a memory system are described. The memory system may perform, on a block of memory cells, a first portion of an erase operation. After performing the first portion of the erase operation, the memory system may receive a write command to write data to the block of memory cells. In response to receiving the write command, the memory system may determine whether a threshold voltage of the block of memory cells satisfies a threshold. In response to determining the that the threshold voltage satisfies the threshold, the memory system may perform a second portion of the erase operation on the block of memory cells. As such, the memory system may write the data to the block of memory cells in response to performing the second portion of the erase operation.

公开(公告)号：US20240232011A1

公开(公告)日：2024-07-11

申请号：US18397889

申请日：2023-12-27

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Amiya Banerjee ,  Nitul Gohain

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F13/1673

Abstract: Methods, systems, and devices for techniques for improved data transfer are described. As part of a data transfer operation from a first set of memory cells of a memory device to a second set of memory cells of the memory device, a memory controller of may read a set of data units from the first set of memory cells. The memory device 240 may transmit the set of data units to the memory controller. The memory controller may decode the set of data units, and, in some cases, may generate one or more corrected data units. The memory controller may then generate parity information for the set of data units, and may encode and write the parity information, along with any corrected data units, to the second set of memory cells of the memory device without transferring the uncorrected data units.

公开(公告)号：US20240345731A1

公开(公告)日：2024-10-17

申请号：US18603031

申请日：2024-03-12

Applicant: Micron Technology, Inc.

Inventor： Jameer Mulani ,  Amiya Banerjee

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for dynamic write speeds for data programming are described. A memory system controller may transfer first data from a first portion of a memory system to a second portion of the memory system according to a first set of parameters based on determining that a first quantity of unavailable data blocks of the first portion satisfies a first threshold. The memory system controller may receive one or more commands to write second data and may write the second data to one or more data blocks of the first portion. The memory system controller may transfer third data from the first portion to the second portion according to a second set of parameters and based on determining that a second quantity of unavailable data blocks of the first portion (and based on writing the second data) satisfies a second threshold.

公开(公告)号：US20240281144A1

公开(公告)日：2024-08-22

申请号：US18437076

申请日：2024-02-08

Applicant: Micron Technology, Inc.

Inventor： Nitul Gohain ,  Jameer Mulani ,  Amiya Banerjee

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: Methods, systems, and devices for techniques for improving host write performance during data transferring (e.g., folding) are described. A memory system may determine to transfer first data from one or more source data blocks of the memory system to one or more destination data blocks, where the source data blocks and the destination data blocks are associated with one or more memory dies of a set of memory dies of the memory system. The memory system may also receive, from a host system, a command to write second data to a first memory die of the one or more memory dies, and write, concurrent with transferring the first data, the second data to a second memory die of the set of memory dies different than the one or more memory dies based on the transfer of the first data being associated with the first memory die.

公开(公告)号：US20240264933A1

公开(公告)日：2024-08-08

申请号：US18424464

申请日：2024-01-26

Applicant: Micron Technology, Inc.

Inventor： Amiya Banerjee ,  Sriraman Sridharan ,  Jameer Mulani

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201

Abstract: Methods, systems, and devices for read performance improvement using memory device latches are described. A memory system may determine whether a portion of an address mapping table is absent from a cache of one or more controllers and may read the portion of the address mapping table from memory cells of the memory device based on the portion of the address mapping table being absent from the cache. The memory system may communicate, to a memory device, a write command to store the portion of the address mapping table in a set of latches of the memory device based on the address mapping table being associated with an access command that is part of a non-sequential read procedure. The memory system may update a tracking table in the cache to indicate that the portion of the address mapping table is stored in the set of latches.

公开(公告)号：US20240268116A1

公开(公告)日：2024-08-08

申请号：US18403266

申请日：2024-01-03

Applicant: Micron Technology, Inc.

Inventor： Amiya Banerjee ,  Kranthi Kumar Vaidyula ,  Davide Resnati ,  Byeung Chul Kim ,  Kyubong Jung ,  Jameer Babasaheb Mulani ,  Jae Kyu Choi ,  Gianpietro Carnevale

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. Channel openings are formed through the first and second tiers. Charge-storage material is formed in the channel openings through the first and second tiers. The charge-storage material comprises a first charge-trap density. The first charge-trap density of the charge-storage material that is in the first tiers is increased as compared to the charge-storage material that is in the second tiers to a second charge-trap density. Channel material is formed in the channel openings through the first and second tiers and that is laterally-inward of the charge-storage material. Other embodiment, including structure, are disclosed.

公开(公告)号：US20240281162A1

公开(公告)日：2024-08-22

申请号：US18434375

申请日：2024-02-06

Applicant: Micron Technology, Inc.

Inventor： Amiya Banerjee ,  Thibash Rajamani Balakrishnan

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0652 ,  G06F3/0604 ,  G06F3/0673

Abstract: Methods, systems, and devices for synchronizing operations between decks of a memory system are described. In some examples, a memory system may determine a PEC difference between sister decks of physical blocks of the memory system. A memory system controller may associate the sister decks with respective virtual blocks. The controller may scan each virtual block of the memory system to determine which blocks are to be recycled, and may generate a list of virtual blocks having a VPC that satisfies a first threshold. In some cases, the controller may perform one or more threshold comparisons to determine whether to perform the maintenance operation on the first sister deck or both the first sister deck and the second sister deck.

公开(公告)号：US20240176550A1

公开(公告)日：2024-05-30

申请号：US18523478

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Gowrishankar Gajendiran ,  Amiya Banerjee

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679

Abstract: Methods, systems, and devices for transferring valid data using a system latch are described. The operations described herein may include sensing valid data across a first set of planes associated with a first set of memory blocks of a non-volatile memory system. In response to sensing the valid data, the valid data may be stored to a latch of the non-volatile memory system based on an order of sensing the valid data across the first set of planes. The valid data may be written across a second set of planes associated with a second set of memory blocks of the non-volatile memory system based on the order of sensing the valid data across the first set of planes. In some cases, writing the valid data from the latch may be based on determining that a threshold associated with a duration corresponding to sensing the valid data has been satisfied.