Invention Publication
- Patent Title: IN-MEMORY COMPUTATION SYSTEM WITH COMPACT STORAGE OF SIGNED COMPUTATIONAL WEIGHT DATA
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Application No.: US17994817Application Date: 2022-11-28
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Publication No.: US20240176586A1Publication Date: 2024-05-30
- Inventor: Marcella CARISSIMI , Paolo Sergio ZAMBOTTI , Riccardo ZURLA
- Applicant: STMicroelectronics S.r.l.
- Applicant Address: IT Agrate Brianza (MB)
- Assignee: STMicroelectronics S.r.l.
- Current Assignee: STMicroelectronics S.r.l.
- Current Assignee Address: IT Agrate Brianza (MB)
- Main IPC: G06F7/544
- IPC: G06F7/544 ; G11C13/00

Abstract:
An IMC circuit includes a memory cells arranged in matrix. Computational weights for an IMC operation are stored in groups of cells. Each row of groups of cells includes a positive and negative word linen. Each column of groups of cells includes a bit line. The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.
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