公开(公告)号：US20240212730A1

公开(公告)日：2024-06-27

申请号：US18542938

申请日：2023-12-18

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella CARISSIMI ,  Marco PASOTTI ,  Riccardo ZURLA

IPC: G11C7/22 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/222 ,  G11C7/12 ,  G11C8/08

Abstract: An in-memory computation device includes a word line activation circuit that receives an input signal indicative of input values and provides activation signals each as a function of the input value. The in-memory computation device further includes a memory array, a biasing circuit generating a bias voltage and a digital detector. The memory array has memory cells coupled to a bit line and each to a word line. Each memory cell stores a computational weight. In response to an activation signal, a cell current flows through each memory cell as a function of the bias voltage, the activation signal and the computational weight. A bit line current flows through the bit line as a function of a summation of the cell currents. The digital detector is coupled to the bit line, samples the bit line current and, in response, provides an output signal.

公开(公告)号：US20240212751A1

公开(公告)日：2024-06-27

申请号：US18543847

申请日：2023-12-18

Applicant: STMicroelectronics S.r.l.

Inventor： Riccardo ZURLA ,  Marco PASOTTI ,  Marcella CARISSIMI ,  Alessandro CABRINI

IPC: G11C13/00 ,  G06F17/16

CPC classification number: G11C13/004 ,  G06F17/16 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/003 ,  G11C2213/79

Abstract: A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.

公开(公告)号：US20240176586A1

公开(公告)日：2024-05-30

申请号：US17994817

申请日：2022-11-28

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella CARISSIMI ,  Paolo Sergio ZAMBOTTI ,  Riccardo ZURLA

IPC: G06F7/544 ,  G11C13/00

CPC classification number: G06F7/5443 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0028

Abstract: An IMC circuit includes a memory cells arranged in matrix. Computational weights for an IMC operation are stored in groups of cells. Each row of groups of cells includes a positive and negative word linen. Each column of groups of cells includes a bit line. The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.