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公开(公告)号：US20230238055A1
公开(公告)日：2023-07-27
申请号：US17582675
申请日：2022-01-24
Inventor： Marco PASOTTI , Marcella CARISSIMI , Antonio GNUDI , Eleonora FRANCHI SCARSELLI , Alessio ANTOLINI , Andrea LICO
IPC: G11C11/4096 , G11C11/408 , G11C11/4094 , G11C11/4074 , G11C11/4076 , G06F7/544
CPC classification number: G11C11/4096 , G11C11/4085 , G11C11/4094 , G11C11/4074 , G11C11/4076 , G06F7/5443
Abstract: A circuit includes a memory array with memory cells arranged in a matrix of rows and columns, where each row includes a word line connected to the memory cells of the row, and each column includes a bit line connected to the memory cells of the column. Computational weights for an in-memory compute operation (IMCO) are stored in the memory cells. A word line control circuit simultaneously actuates word lines in response to input signals providing coefficient data for the IMCO by applying word line signal pulses. A column processing circuit connected to the bit lines processes analog signals developed on the bit lines in response to the simultaneous actuation of the word lines to generate multiply and accumulate output signals for the IMCO. Pulse widths of the signal pulses are modulated to compensate for cell drift. The IMCO further handles positive/negative calculation for the coefficient data and computational weights.
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公开(公告)号：US20240176586A1
公开(公告)日：2024-05-30
申请号：US17994817
申请日：2022-11-28
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella CARISSIMI , Paolo Sergio ZAMBOTTI , Riccardo ZURLA
CPC classification number: G06F7/5443 , G11C13/0004 , G11C13/0026 , G11C13/0028
Abstract: An IMC circuit includes a memory cells arranged in matrix. Computational weights for an IMC operation are stored in groups of cells. Each row of groups of cells includes a positive and negative word linen. Each column of groups of cells includes a bit line. The IMC operation includes a first elaboration where a word line signal is applied to the positive/negative word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a positive MAC output on the bit line. In a second elaboration, a word line signal is applied to the negative/positive word line of the group of cells depending on the positive/negative sign, respectively, of the coefficient data, with a negative MAC output on the bit line. The IMC operation result is obtained from a difference between the positive and negative MAC operations.
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公开(公告)号：US20220068395A1
公开(公告)日：2022-03-03
申请号：US17407903
申请日：2021-08-20
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella CARISSIMI , Fabio Enrico Carlo DISEGNI , Chantal AURICCHIO , Cesare TORTI , Davide MANFRE' , Laura CAPECCHI , Emanuela CALVETTI , Stefano ZANCHI
Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.
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4.发明申请ERROR CORRECTION IN DIFFERENTIAL MEMORY DEVICES WITH READING IN SINGLE-ENDED MODE IN ADDITION TO READING IN DIFFERENTIAL MODE 有权在具有读取单边模式的差异存储器件中的错误校正，以便在差异模式下读取公开(公告)号：US20150212880A1
公开(公告)日：2015-07-30
申请号：US14597824
申请日：2015-01-15
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Marcella CARISSIMI , Marco PASOTTI
CPC classification number: G11C29/52 , G06F11/1048 , G11C7/18 , G11C11/5642 , G11C16/0441 , G11C16/26 , G11C16/28 , G11C2211/4013
Abstract: A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.
Abstract translation: 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。
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5.发明公开公开(公告)号：US20240212751A1
公开(公告)日：2024-06-27
申请号：US18543847
申请日：2023-12-18
Applicant: STMicroelectronics S.r.l.
Inventor： Riccardo ZURLA , Marco PASOTTI , Marcella CARISSIMI , Alessandro CABRINI
CPC classification number: G11C13/004 , G06F17/16 , G11C13/0004 , G11C13/0028 , G11C13/003 , G11C2213/79
Abstract: A word line activation unit of an in-memory computation generates activation signals as a function of an input value. The in-memory computation device includes a memory array with a plurality of memory cells (each storing a computational weight) coupled to a bit line and each to a word line and a digital detector. A cell current flows through each memory cell as a function of the activation signal and the computational weight and a bit line current is generated as a function of a summation of the cell currents. The digital detector performs successive iterations on the bit line current. In each iteration: an integration stage generates an integration signal indicative of a time integral of the bit line current, and resets the integration signal when the integration signal reaches a threshold; and the counter stage updates the output signal in response to the integration signal reaching the threshold.
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Patent Agency Ranking
公开(公告)号：US20230326524A1
公开(公告)日：2023-10-12
申请号：US17718908
申请日：2022-04-12
Inventor： Marco PASOTTI , Marcella CARISSIMI , Alessio ANTOLINI , Eleonora FRANCHI SCARSELLI , Antonio GNUDI , Andrea LICO , Paolo ROMELE
IPC: G11C13/00
CPC classification number: G11C13/0061 , G11C13/0004 , G11C13/0026 , G11C13/0038
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
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公开(公告)号：US20230245699A1
公开(公告)日：2023-08-03
申请号：US18148380
申请日：2022-12-29
Applicant: STMICROELECTRONICS S.r.l.
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C13/0004 , G11C2013/0045 , G11C2013/0054
Abstract: The present disclosure is directed to a sense amplifier architecture for a memory device having a plurality of memory cells. Groups of non-volatile memory cells store respective codewords formed by stored logic states, logic high or logic low, of the memory cells of the group. The sense amplifier architecture has a plurality of sense amplifier reading branches, each sense amplifier reading branch coupled to a respective memory cell and configured to provide an output signal, which is indicative of a cell current flowing through the same memory cell; a comparison stage, to perform a comparison between the cell currents of memory cells of a group; and a logic stage, to determine, based on comparison results provided by the comparison stage, a read codeword corresponding to the group of memory cells. Information may be stored in different subsets of codewords, the sense amplifier architecture in this case having a subset definition circuit, to allow a preliminary determination of the subset to which a codeword to be read belongs to, based on reference signals.
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公开(公告)号：US20240212730A1
公开(公告)日：2024-06-27
申请号：US18542938
申请日：2023-12-18
Applicant: STMicroelectronics S.r.l.
Inventor： Marcella CARISSIMI , Marco PASOTTI , Riccardo ZURLA
Abstract: An in-memory computation device includes a word line activation circuit that receives an input signal indicative of input values and provides activation signals each as a function of the input value. The in-memory computation device further includes a memory array, a biasing circuit generating a bias voltage and a digital detector. The memory array has memory cells coupled to a bit line and each to a word line. Each memory cell stores a computational weight. In response to an activation signal, a cell current flows through each memory cell as a function of the bias voltage, the activation signal and the computational weight. A bit line current flows through the bit line as a function of a summation of the cell currents. The digital detector is coupled to the bit line, samples the bit line current and, in response, provides an output signal.
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公开(公告)号：US20230326499A1
公开(公告)日：2023-10-12
申请号：US17718755
申请日：2022-04-12
Inventor： Marco PASOTTI , Marcella CARISSIMI , Alessio ANTOLINI , Eleonora FRANCHI SCARSELLI , Antonio GNUDI , Andrea LICO
CPC classification number: G11C7/1063 , G11C7/12 , G11C8/08 , G11C7/14 , G11C7/16
Abstract: An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A switching circuit is connected between each bit line and a corresponding column output. The switching circuit is controlled to turn on to generate the analog signal dependent on the computational weight and for a time duration controlled by the coefficient data signal. A column combining circuit combines (by addition and/or subtraction) and integrates analog signals at the column outputs of the biasing circuits. The addition/subtraction is dependent on one or more a sign of the coefficient data and a sign of the computational weight and may further implement a binary weighting function.
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10.发明公开公开(公告)号：US20230223079A1
公开(公告)日：2023-07-13
申请号：US18148378
申请日：2022-12-29
Applicant: STMICROELECTRONICS S.r.l.
CPC classification number: G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/004 , G11C2013/0054
Abstract: The present disclosure is directed to a method for storing information in a coded manner in non-volatile memory cells. The method includes providing a group of non-volatile memory cells of non volatile memory. The memory cell is of the type in which a stored logic state, which can be logic high or logic low, can be changed through application of a current to the cell and the state in the memory cell is read by reading a current provided by the cell. The group of non-volatile memory cells include a determined number of non-volatile memory cells which is greater than two. The group of non-volatile memory cells store a codeword formed by the values of said stored states of the cells of the group taken according to a given order. Given a set of codewords obtainable by the stored values in the determined number of non-volatile memory cells in a group, the method includes storing the information in at least two subsets of said set of codewords comprising each at least a codeword. Each codeword in a same subset has a same Hamming weight. Each codeword belonging to one subset has a Hamming distance equal or greater than two with respect to each codeword belonging to another subset.
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