Invention Publication
- Patent Title: INTEGRATED CIRCUIT STRUCTURES WITH SOURCE OR DRAIN CONTACTS HAVING ENHANCED CONTACT AREA
-
Application No.: US18072559Application Date: 2022-11-30
-
Publication No.: US20240178273A1Publication Date: 2024-05-30
- Inventor: Chiao-Ti HUANG , Tao CHU , Guowei XU , Chung-Hsun LIN , Brian Greene
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L23/48 ; H01L27/088 ; H01L29/417 ; H01L29/786

Abstract:
Integrated circuit structures having source or drain contacts with enhanced contact area, and methods of fabricating integrated circuit structures having source or drain contacts with enhanced contact area, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive contact structure is vertically over the epitaxial source or drain structure. The conductive contact structure has a lower portion extending over the top and along upper portions of sides of the epitaxial source or drain structure, and has an upper portion on the lower portion. The upper portion has a maximum lateral width less than a maximum lateral width of the lower portion.
Information query
IPC分类: