公开(公告)号：US20230307449A1

公开(公告)日：2023-09-28

申请号：US17656490

申请日：2022-03-25

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Aurelia Chi Wang ,  Conor Puls ,  Brian Greene ,  Tofizur Rahman ,  Lin Hu ,  Jaladhi Mehta ,  Chung-Hsun Lin ,  Walid Hafez

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L27/088 ,  H01L29/0665 ,  H01L29/42392

Abstract: An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).

公开(公告)号：US20240088132A1

公开(公告)日：2024-03-14

申请号：US17943819

申请日：2022-09-13

Applicant: Intel Corporation

Inventor： Nicholas A. Thomson ,  Kalyan C. Kolluru ,  Ayan Kar ,  Chu-Hsin Liang ,  Benjamin Orr ,  Biswajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Sabih U. Omar ,  Sameer Jayanta Joglekar

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L29/0673 ,  H01L29/8611

Abstract: An integrated circuit structure includes a sub-fin having (i) a first portion including a p-type dopant and (ii) a second portion including an n-type dopant. A first body of semiconductor material is above the first portion of the sub-fin, and a second body of semiconductor material is above the second portion of the sub-fin. In an example, the first portion of the sub-fin and the second portion of the sub-fin are in contact with each other, to form a PN junction of a diode. For example, the first portion of the sub-fin is part of an anode of the diode, and wherein the second portion of the sub-fin is part of a cathode of the diode.

公开(公告)号：US20220199472A1

公开(公告)日：2022-06-23

申请号：US17132995

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Robin Chao ,  Bishwajeet Guha ,  Brian Greene ,  Chung-Hsun Lin ,  Curtis Tsai ,  Orb Acton

IPC: H01L21/8234 ,  H01L27/088 ,  H01L27/12 ,  H01L21/84

Abstract: Integrated circuitry comprising high voltage (HV) and low voltage (LV) ribbon or wire (RoW) transistor stack structures. In some examples, a gate electrode of the HV and LV transistor stack structures may include the same work function metal. A metal oxide may be deposited around one or more channels of the HV transistor stack, thereby altering the dipole properties of the gate insulator stack from those of the LV transistor stack structure.

公开(公告)号：US20210408289A1

公开(公告)日：2021-12-30

申请号：US16914145

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Brian Greene ,  Robin Chao ,  Adam Faust ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

公开(公告)号：US20240334669A1

公开(公告)日：2024-10-03

申请号：US18129717

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Akitomo Matsubayashi ,  Brian Greene ,  Chung-Hsun Lin

IPC: H10B10/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785

Abstract: An apparatus comprising a source or drain of a field effect transistor (FET), a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride, and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.

公开(公告)号：US20240290835A1

公开(公告)日：2024-08-29

申请号：US18174007

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Guowei Xu ,  Tao Chu ,  Robin Chao ,  Jaladhi Mehta ,  Brian Greene ,  Chung-Hsun Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.

公开(公告)号：US11417781B2

公开(公告)日：2022-08-16

申请号：US16830112

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US12166031B2

公开(公告)日：2024-12-10

申请号：US17131616

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Brian Greene ,  Daniel Schulman ,  William Hsu ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/87

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

公开(公告)号：US20240178273A1

公开(公告)日：2024-05-30

申请号：US18072559

申请日：2022-11-30

Applicant: Intel Corporation

Inventor： Chiao-Ti HUANG ,  Tao CHU ,  Guowei XU ,  Chung-Hsun LIN ,  Brian Greene

IPC: H01L29/06 ,  H01L23/48 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L23/481 ,  H01L27/0886 ,  H01L29/41733 ,  H01L29/78696

Abstract: Integrated circuit structures having source or drain contacts with enhanced contact area, and methods of fabricating integrated circuit structures having source or drain contacts with enhanced contact area, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive contact structure is vertically over the epitaxial source or drain structure. The conductive contact structure has a lower portion extending over the top and along upper portions of sides of the epitaxial source or drain structure, and has an upper portion on the lower portion. The upper portion has a maximum lateral width less than a maximum lateral width of the lower portion.

公开(公告)号：US11869987B2

公开(公告)日：2024-01-09

申请号：US17860056

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/93 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/93 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/66174

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.