Invention Publication
- Patent Title: INTEGRATED SEMICONDUCTOR DIE PARCELING PLATFORMS
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Application No.: US18513542Application Date: 2023-11-18
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Publication No.: US20240190596A1Publication Date: 2024-06-13
- Inventor: Tsung-Sheng KUO , Hsu-Shui LIU , Jiun-Rong PAI , Yang-Ann CHU , Chieh-Chun LIN , Shine CHEN
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- The original application number of the division: US17686299 2022.03.03
- Main IPC: B65B5/04
- IPC: B65B5/04 ; B65G47/28 ; G01N21/95 ; G06T7/00

Abstract:
In certain embodiments, a system includes: an inspection station configured to receive a die vessel, wherein the inspection station is configured to inspect the die vessel for defects; a desiccant station configured to receive the die vessel from the inspection station, wherein the desiccant station is configured to add a desiccant to the die vessel; a bundle station configured to receive the die vessel from the desiccant station, wherein the bundle station is configured to combine the die vessel with another die vessel as a die bundle; and a bagging station configured to receive the die bundle from the bundle station, wherein the bagging station is configured to dispose the die bundle in a die bag and to heat seal the die bag with the die bundle inside.
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