- 专利标题: SHARED CLOCK DUAL EDGE-TRIGGERED FLIP-FLOP CIRCUIT
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申请号: US18081907申请日: 2022-12-15
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公开(公告)号: US20240204782A1公开(公告)日: 2024-06-20
- 发明人: Amit Agarwal , Steven K. Hsu , Ram Kumar Krishnamurthy
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 主分类号: H03K19/094
- IPC分类号: H03K19/094 ; H03K19/017 ; H03K19/1776
摘要:
Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.
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