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公开(公告)号：US20240319269A1
公开(公告)日：2024-09-26
申请号：US18124338
申请日：2023-03-21
申请人： Intel Corporation
IPC分类号： G01R31/317 , G01R31/3185
CPC分类号： G01R31/31725 , G01R31/31713 , G01R31/318536
摘要： An apparatus includes a plurality of delay generators, a first plurality of flip-flop circuits, a second plurality of flip-flop circuits, and a third plurality of flip-flop circuits. The plurality of delay generators includes a data delay generator, an enable delay generator, and a reference delay generator. The first plurality of flip-flop circuits is coupled to the data delay generator to receive a delayed data input signal, and provide the delayed data input signal to a plurality of data input terminals of a memory circuit. The second plurality of flip-flop circuits is coupled to the enable delay generator to receive a delayed enable signal and provide the delayed enable signal to a plurality of enable terminals of the memory circuit. The third plurality of flip-flop circuits is coupled to an output terminal of the memory circuit. The reference delay generator provides a synchronized clock signal to the flip-flop circuits.
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公开(公告)号：US20230195388A1
公开(公告)日：2023-06-22
申请号：US17555174
申请日：2021-12-17
申请人： Intel Corporation
发明人： William Butera , David Webb , Mitchell Diamond , Steven Hsu , Amit Agarwal
CPC分类号： G06F3/0667 , G06F9/3818 , G06F3/0604 , G06F3/0673
摘要： Methods and apparatus relating to register file virtualization techniques are described. In an embodiment, a register file includes a plurality of register file cells. Each of the register file cells includes a register file entry and a shadow buffer. Logic circuitry causes storage of input data to the shadow buffer, while data stored in the register file entry is accessible to perform one or more operations. Other embodiments are also disclosed and claimed.
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公开(公告)号：US11054470B1
公开(公告)日：2021-07-06
申请号：US16725689
申请日：2019-12-23
申请人： Intel Corporation
IPC分类号： G01R31/3185 , G01R31/317 , H03K3/037 , G01R31/3177 , H03K3/038
摘要： A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.
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公开(公告)号：US20210203323A1
公开(公告)日：2021-07-01
申请号：US16727742
申请日：2019-12-26
申请人： Intel Corporation
发明人： Steven Hsu , Amit Agarwal , Simeon Realov , Ram Krishnamurthy
摘要： A parasitic-aware single-edge triggered flip-flop reduces clock power through layout optimization, enabled through process-circuit co-optimization. The static pass-gate master-slave flip-flop utilizes novel layout optimization enabling significant power reduction. The layout removes the clock poly over notches in the diffusion area. Poly lines implement clock nodes. The poly lines are aligned between n-type and p-type active regions.
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公开(公告)号：US10756736B2
公开(公告)日：2020-08-25
申请号：US16335092
申请日：2017-08-30
申请人： Intel Corporation
IPC分类号： H03K19/0185 , H03K3/037
摘要： Some embodiments include apparatus and methods using an input stage and an output stage of a circuit. The input stage operates to receive an input signal and a clock signal and to provide an internal signal at an internal node based at least in part on the input signal. The input signal has levels in a first voltage range. The internal signal has levels in a second voltage range greater than the first voltage range. The output stage operates to receive the internal signal, the clock signal, and an additional signal generated based on the input signal. The output stage provides an output signal based at least in part on the input signal and the additional signal. The output signal has a third voltage range greater than the first voltage range.
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公开(公告)号：US10193536B2
公开(公告)日：2019-01-29
申请号：US15860562
申请日：2018-01-02
申请人： INTEL CORPORATION
IPC分类号： H03K3/3562 , H03K3/037
摘要： An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared p-type keeper coupled to an output of the first inverter, the master latch coupled to the data node; and a slave latch coupled to an output of the master latch, the slave latch having a shared p-type keeper and a shared n-type footer, wherein the shared p-type keeper and the shared n-type footer of the slave latch are coupled to the clock node and the input of the first inverter.
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7.发明授权公开(公告)号：US09960753B2
公开(公告)日：2018-05-01
申请号：US15209531
申请日：2016-07-13
申请人： Intel Corporation
IPC分类号： H03K3/289 , H03K3/3562 , H03K3/356
CPC分类号： H03K3/35625 , H03K3/356104
摘要： Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.
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8.发明授权Apparatus and method for low power fully-interruptible latches and master-slave flip-flops 有权低功耗全中断锁存器和主从触发器的装置和方法公开(公告)号：US09035686B1
公开(公告)日：2015-05-19
申请号：US14069198
申请日：2013-10-31
申请人： Intel Corporation
CPC分类号： H03K3/35625 , H03K3/356104
摘要： Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.
摘要翻译： 描述了一种锁存器，其包括：第一AND-OR反相（AOI）逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源节点的相应的第一和第二保持器装置。 描述了一种触发器，其包括：第一锁存器，包括：第一AOI逻辑门; 以及耦合到所述第一AOI逻辑门的第二AOI逻辑门，其中所述第一和第二AOI逻辑门具有耦合到电源的相应的第一和第二保持器装置，所述第一锁存器具有输出节点; 以及第二锁存器，其具有耦合到所述第一锁存器的输出节点的输入节点，所述第二锁存器具有输出节点以提供所述触发器的输出。
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9.发明公开公开(公告)号：US20240223167A1
公开(公告)日：2024-07-04
申请号：US18091970
申请日：2022-12-30
申请人： Intel Corporation
摘要： Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to “1” when a clock signal is “0.” In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.
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公开(公告)号：US11296681B2
公开(公告)日：2022-04-05
申请号：US16726020
申请日：2019-12-23
申请人： Intel Corporation
IPC分类号： H03K3/00 , H03K3/037 , G01R31/3177 , H03K3/038 , H03K19/20
摘要： A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.
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