Systems, methods, and apparatus related to memory devices. In one approach, a memory device uses an architecture having a precharge transistor in parallel with a cascode transistor. The precharge transistor (e.g., a p-channel device) performs precharging of a bitline to a fixed constant voltage in preparation for sensing a memory cell. The cascode transistor (e.g., an n-channel device) is used to determine the voltage of the bitline during sensing and discharges a sensing node if the memory cell switches (e.g., snaps). The sensing node is coupled to an input of a detector that determines the logic state of the memory cell.