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    MEMORY DEVICE TO SENSE MEMORY CELLS WITHOUT BITLINE PRECHARGE
    1.
    发明公开
    MEMORY DEVICE TO SENSE MEMORY CELLS WITHOUT BITLINE PRECHARGE 审中-公开

    公开(公告)号：US20240212750A1

    公开(公告)日：2024-06-27

    申请号：US18536098

    申请日：2023-12-11

    Applicant: Micron Technology, Inc.

    Inventor： Michele Maria Venturini ,  Umberto di Vincenzo

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device controls a power supply to a detector that is used to sense a voltage of a bitline coupled to a memory cell. An output of the detector indicates a logic state of the selected memory cell. By controlling a voltage of the power supply, a detection threshold of the detector can be increased as the voltage on the bitline increases. This permits the detector to be used without requiring precharge of the bitline.

    COUNTER-BASED METHODS AND SYSTEMS FOR ACCESSING MEMORY CELLS
    3.
    发明公开
    COUNTER-BASED METHODS AND SYSTEMS FOR ACCESSING MEMORY CELLS 审中-公开

    公开(公告)号：US20240134533A1

    公开(公告)日：2024-04-25

    申请号：US18396414

    申请日：2023-12-26

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

    IPC: G06F3/06

    CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0679

    Abstract: A method including storing user data in memory cells of a memory array, storing, in a counter associated to the memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data, applying the read voltage to the cells of the counter to read the count data and to provide a target value corresponding to the number of bits in the user data having the first logic value. During the application of the read voltage, the count data and the user data are read simultaneously such that the target value is provided during the reading of the user data. The application of the read voltage is stopped when the number of bits in the user data having the first logic value corresponds to the target value.

    Cascoded sense amplifiers for self-selecting memory
    5.
    发明授权
    Cascoded sense amplifiers for self-selecting memory 有权

    公开(公告)号：US12300316B2

    公开(公告)日：2025-05-13

    申请号：US17896963

    申请日：2022-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Umberto di Vincenzo ,  Ferdinando Bedeschi ,  Michele Maria Venturini ,  Claudia Palattella

    IPC: G11C13/00

    Abstract: Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.

    Refresh determination using memory cell patterns
    6.
    发明授权
    Refresh determination using memory cell patterns 有权

    公开(公告)号：US12236992B2

    公开(公告)日：2025-02-25

    申请号：US17852221

    申请日：2022-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Umberto di Vincenzo ,  Ferdinando Bedeschi ,  Christian Marc Benoit Caillat

    IPC: G11C11/40 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096

    Abstract: A system includes a memory array having pattern cells and data cells. The pattern cells are configured to store only a first logic state. The data cells are configured to store the first logic state or a second logic state. Bias circuitry is configured to apply voltages to the pattern cells and data cells. Sensing circuitry is configured to read the pattern cells. A controller is configured to apply, using the bias circuitry, first voltages to the pattern cells; determine, using the sensing circuitry, that at least a portion of the pattern cells switch; determine, based on the portion of the pattern cells that switch, to refresh a codeword; and apply, using the bias circuitry, the refresh of the codeword.

    Counter-based methods and systems for accessing memory cells
    7.
    发明授权
    Counter-based methods and systems for accessing memory cells 有权

    公开(公告)号：US11880571B2

    公开(公告)日：2024-01-23

    申请号：US17044150

    申请日：2020-05-13

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

    IPC: G06F3/06

    CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0653 ,  G06F3/0679

    Abstract: The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value corresponds to the target value. A related memory device and a related system are also disclosed.

    Architecture for multideck memory arrays
    10.
    发明授权
    Architecture for multideck memory arrays 有权

    公开(公告)号：US11963370B2

    公开(公告)日：2024-04-16

    申请号：US17043392

    申请日：2020-03-03

    Applicant: Micron Technology, Inc.

    Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto di Vincenzo

    IPC: H10B63/00 ,  G11C13/00 ,  H10N70/20

    CPC classification number: H10B63/84 ,  G11C13/0004 ,  G11C13/003 ,  H10N70/231 ,  G11C2213/71

    Abstract: The present disclosure relates to a memory device comprising an array of memory cells arranged in a multideck configuration comprising a plurality of superimposed decks, a plurality of access lines comprising at least a first plurality of access lines arranged in a first level, a second plurality of access lines arranged in a second level, and a third plurality of access lines arranged in a third level between the first plurality of access lines and the second plurality of access lines, the third plurality of access lines being arranged between two decks of the plurality of decks, a plurality of drivers configured to drive signals to the access lines, and connection elements configured to electrically connect the access lines to the respective drivers. The connections elements and the access lines are arranged so that a single driver of the plurality of drivers is configured to drive at least one access line of each level of the at least three levels. Related memory systems and methods are also disclosed.

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