- 专利标题： CHIP-SCALE PACKAGE ARCHITECTURES CONTAINING A DIE BACK SIDE METAL AND A SOLDER THERMAL INTERFACE MATERIAL
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申请号： US18744108申请日： 2024-06-14
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公开(公告)号： US20240332112A1公开(公告)日： 2024-10-03
- 发明人: Susmriti Das Mahapatra , Malavarayan Sankarasubramanian , Shenavia Howell , John Harper , Mitul Modi
- 申请人： Intel Corporation
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 主分类号： H01L23/36
- IPC分类号： H01L23/36 ; H01L21/48 ; H01L21/50 ; H01L21/60 ; H01L21/768 ; H01L23/00 ; H01L23/367 ; H01L23/373 ; H01L23/42 ; H01L23/488
摘要：
An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.
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