Invention Publication
- Patent Title: ERROR DETECTION IN CRYPTOGRAPHIC SUBSTITUTION BOX OPERATIONS
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Application No.: US18194270Application Date: 2023-03-31
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Publication No.: US20240333472A1Publication Date: 2024-10-03
- Inventor: Raghavan Kumar , Sanu Mathew , Avinash V. Varna , Kirk S. YAP
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H04L9/06
- IPC: H04L9/06

Abstract:
An apparatus of an aspect includes a substitution box (S-box) circuitry. The S-box circuitry includes multiplicative inverse circuitry. The multiplicative inverse circuitry is to receive an 8-bit input in Galois field and is to generate a corresponding 8-bit output in Galois field. The 8-bit output is to be a multiplicative inverse of the 8-bit input as long as there has been no error in the generation of the 8-bit output. The apparatus also includes error detection circuitry to receive the 8-bit input and that is coupled with the S-box circuitry to receive the 8-bit output. The error detection circuitry to detect whether an error has occurred in the generation of the 8-bit output based at least in part on whether the 8-bit output is the multiplicative inverse of the 8-bit input. Other apparatus, methods, and systems are also disclosed.
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