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    OPTIMIZATION TECHNIQUE FOR MODULAR MULTIPLICATION ALGORITHMS
    2.
    发明公开
    OPTIMIZATION TECHNIQUE FOR MODULAR MULTIPLICATION ALGORITHMS 审中-公开

    公开(公告)号：US20230401037A1

    公开(公告)日：2023-12-14

    申请号：US18237859

    申请日：2023-08-24

    Applicant: Intel Corporation

    Inventor： Erdinc OZTURK ,  Kirk S. YAP ,  Tomasz KANTECKI

    IPC: G06F7/72

    CPC classification number: G06F7/722 ,  G06F7/728

    Abstract: Methods and apparatus for optimization techniques for modular multiplication algorithms. The optimization techniques may be applied to variants of modular multiplication algorithms, including variants of Montgomery multiplication algorithms and Barrett multiplication algorithms. The optimization techniques reduce the number of serial steps in Montgomery reduction and Barrett reduction. Modular multiplication operations involving products of integer inputs A and B may be performed in parallel to obtain a value C that is reduced to a residual RES. Modular multiplication and modular reduction operations may be performed in parallel. The number of serial steps in the modular reductions are reduced to L, where L serial steps, where w is a digit size in bits, and L is a number of digits of operands=[k/w].

    MEMORY BUS INTEGRITY AND DATA ENCRYPTION (IDE)
    3.
    发明申请
    MEMORY BUS INTEGRITY AND DATA ENCRYPTION (IDE) 有权

    公开(公告)号：US20210336767A1

    公开(公告)日：2021-10-28

    申请号：US17359152

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Raghunandan MAKARAM ,  Kirk S. YAP ,  Rajat AGARWAL ,  George VERGIS ,  Bill NALE ,  Jacob DOWECK

    IPC: H04L9/06 ,  H04L9/08 ,  H04L9/32 ,  G11C29/42 ,  G11C29/12

    Abstract: A memory subsystem includes link encryption for the system memory data bus. The memory controller can provide encryption for data at rest and link protection. The memory controller can optionally provide link encryption. Thus, the system can provide link protection for the data in transit. The memory module can include a link decryption engine that can decrypt link encryption if it is used, and performs a link integrity check with a link integrity tag associated with the link protection. The memory devices can then store the encrypted protected data and ECC data from the link decryption engine after link protection verification.

    PROCESS-BASED MULTI-KEY TOTAL MEMORY ENCRYPTION
    4.
    发明申请
    PROCESS-BASED MULTI-KEY TOTAL MEMORY ENCRYPTION 有权

    公开(公告)号：US20210149704A1

    公开(公告)日：2021-05-20

    申请号：US17127729

    申请日：2020-12-18

    Applicant: Intel Corporation

    Inventor： Wajdi FEGHALI ,  Vinodh GOPAL ,  Kirk S. YAP ,  Sean GULLEY ,  Raghunandan MAKARAM

    IPC: G06F9/455 ,  G06F12/14 ,  H04L9/08

    Abstract: Systems, methods, and circuitries are disclosed for a per-process memory encryption system. At least one translation lookaside buffer (TLB) is configured to encode key identifiers for keys in one or more bits of either the virtual memory address or the physical address. The process state memory configured to store a first process key table for a first process that maps key identifiers to unique keys and a second process key table that maps the key identifiers to different unique keys. The active process key table memory configured to store an active key table. In response to a request for data corresponding to a virtual memory address, the at least one TLB is configured to provide a key identifier for the data to the active process key table to cause the active process key table to return the unique key mapped to the key identifier.

    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS
    5.
    发明申请
    INSTRUCTIONS PROCESSORS, METHODS, AND SYSTEMS TO PROCESS SECURE HASH ALGORITHMS 审中-公开

    公开(公告)号：US20200280432A1

    公开(公告)日：2020-09-03

    申请号：US16807021

    申请日：2020-03-02

    Applicant: Intel Corporation

    Inventor： Gilbert M. WOLRICH ,  Kirk S. YAP ,  Vinodh GOPAL ,  James D. GUILFORD

    IPC: H04L9/06 ,  G06F21/64 ,  G06F9/30 ,  G06F21/72 ,  G06F21/60

    Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements ai, bi, ei, and fi for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements ai, bi, ci, di, ei, fi, gi, hi of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements ai+, bi+, ei+, and fi+ that have been updated from the corresponding state data elements ai, bi, ei, and fi by at least one round of the SHA2 hash algorithm.

    System, Apparatus And Method For Providing Protection Against Silent Data Corruption In A Link
    7.
    发明申请
    System, Apparatus And Method For Providing Protection Against Silent Data Corruption In A Link 有权

    公开(公告)号：US20250117285A1

    公开(公告)日：2025-04-10

    申请号：US18974396

    申请日：2024-12-09

    Applicant: Intel Corporation

    Inventor： Raghunandan MAKARAM ,  Kirk S. YAP

    IPC: G06F11/10 ,  H04L9/32 ,  H04L69/22

    Abstract: In one embodiment, an apparatus includes: an integrity circuit to receive data and generate a protection code based at least in part on the data; a cryptographic circuit coupled to the integrity circuit to encrypt the data into encrypted data and encrypt the protection code into an encrypted protection code; a message authentication code (MAC) circuit coupled to the cryptographic circuit to compute a MAC comprising a tag using header information, the encrypted data, and the encrypted protection code; and an output circuit to send the header information, the encrypted data, and the tag to a receiver via a link. Other embodiments are described and claimed.

    ERROR DETECTION IN CRYPTOGRAPHIC SUBSTITUTION BOX OPERATIONS
    10.
    发明公开
    ERROR DETECTION IN CRYPTOGRAPHIC SUBSTITUTION BOX OPERATIONS 审中-公开

    公开(公告)号：US20240333472A1

    公开(公告)日：2024-10-03

    申请号：US18194270

    申请日：2023-03-31

    Applicant: Intel Corporation

    Inventor： Raghavan Kumar ,  Sanu Mathew ,  Avinash V. Varna ,  Kirk S. YAP

    IPC: H04L9/06

    CPC classification number: H04L9/0631 ,  H04L9/0637

    Abstract: An apparatus of an aspect includes a substitution box (S-box) circuitry. The S-box circuitry includes multiplicative inverse circuitry. The multiplicative inverse circuitry is to receive an 8-bit input in Galois field and is to generate a corresponding 8-bit output in Galois field. The 8-bit output is to be a multiplicative inverse of the 8-bit input as long as there has been no error in the generation of the 8-bit output. The apparatus also includes error detection circuitry to receive the 8-bit input and that is coupled with the S-box circuitry to receive the 8-bit output. The error detection circuitry to detect whether an error has occurred in the generation of the 8-bit output based at least in part on whether the 8-bit output is the multiplicative inverse of the 8-bit input. Other apparatus, methods, and systems are also disclosed.

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