公开(公告)号：US20240333472A1

公开(公告)日：2024-10-03

申请号：US18194270

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Sanu Mathew ,  Avinash V. Varna ,  Kirk S. YAP

IPC: H04L9/06

CPC classification number: H04L9/0631 ,  H04L9/0637

Abstract: An apparatus of an aspect includes a substitution box (S-box) circuitry. The S-box circuitry includes multiplicative inverse circuitry. The multiplicative inverse circuitry is to receive an 8-bit input in Galois field and is to generate a corresponding 8-bit output in Galois field. The 8-bit output is to be a multiplicative inverse of the 8-bit input as long as there has been no error in the generation of the 8-bit output. The apparatus also includes error detection circuitry to receive the 8-bit input and that is coupled with the S-box circuitry to receive the 8-bit output. The error detection circuitry to detect whether an error has occurred in the generation of the 8-bit output based at least in part on whether the 8-bit output is the multiplicative inverse of the 8-bit input. Other apparatus, methods, and systems are also disclosed.