Invention Publication
- Patent Title: THROUGH-SILICON VIA DIE
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Application No.: US18140146Application Date: 2023-04-27
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Publication No.: US20240363490A1Publication Date: 2024-10-31
- Inventor: Mohammad Enamul KABIR , Keith ZAWADZKI , Rahim KASIM , Sunny CHUGH , Zhizheng ZHANG , Christopher M. PELTO , Babita DHAYAL , John Kevin TAYLOR , Doug INGERLY
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L21/768 ; H01L23/00 ; H01L23/498 ; H01L23/58 ; H01L29/06

Abstract:
Through-silicon via dies are described. In an example, a semiconductor die includes a substrate having a device side and a backside. An active device layer is in or on the device side of the substrate. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the substrate. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of through silicon vias is in the substrate and extend into the dielectric structure and are connected to the plurality of metallization layers. A plurality of backside metallization structures is beneath the backside of the substrate. The plurality of through silicon vias are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.
Information query
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