Invention Application
- Patent Title: TUNING GATE LENGTHS IN MULTI-GATE FIELD EFFECT TRANSISTORS
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Application No.: US18782515Application Date: 2024-07-24
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Publication No.: US20240379801A1Publication Date: 2024-11-14
- Inventor: Chia-Hao Pao , Chih-Chuan Yang , Shih-Hao Lin , Kian-Long Lim , Chih-Hsuan Chen , Ping-Wei Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L21/265 ; H01L21/308 ; H01L29/06 ; H01L29/40 ; H01L29/417 ; H01L29/66 ; H01L29/786

Abstract:
A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.
Information query
IPC分类: