公开(公告)号：US20240379444A1

公开(公告)日：2024-11-14

申请号：US18772215

申请日：2024-07-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien-Jung Hung

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US12016169B2

公开(公告)日：2024-06-18

申请号：US17842208

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426 ,  H10B10/00 ,  H10B41/35

CPC classification number: H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H01L22/12 ,  H01L23/528 ,  H04N21/42692 ,  H10B10/00 ,  H10B41/35 ,  G11C2213/74 ,  G11C2213/79 ,  H01L2924/1437

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

公开(公告)号：US11791214B2

公开(公告)日：2023-10-17

申请号：US17387636

申请日：2021-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien Jung Hung

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66742 ,  H01L29/7851 ,  H01L29/78696

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US20230217640A1

公开(公告)日：2023-07-06

申请号：US18182837

申请日：2023-03-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chia-Wei Chen ,  Chien-Chih Lin

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/775 ,  H01L29/423 ,  H10B10/00

CPC classification number: H01L29/0673 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/42392 ,  H10B10/125

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

公开(公告)号：US20220367656A1

公开(公告)日：2022-11-17

申请号：US17387636

申请日：2021-07-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien Jung Hung

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US20220310630A1

公开(公告)日：2022-09-29

申请号：US17842208

申请日：2022-06-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H01L23/528 ,  H01L27/11524 ,  H04N21/426

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

公开(公告)号：US12080342B2

公开(公告)日：2024-09-03

申请号：US17698681

申请日：2022-03-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Jui-Wen Chang ,  Chao-Yuan Chang ,  Feng-Ming Chang ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: A memory device is provided. The memory device includes a memory cell array having a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of columns include a first plurality of memory cells connected to a first bit line and a second bit line. A pre-charge circuit is connected to the memory cell array. The pre-charge circuit pre-charges each of the first bit line and the second bit line from a first end. A pre-charge assist circuit is connected to the memory cell array. The pre-charge assist circuit pre-charges each of the first bit line and the second bit line from a second end, the second end being opposite the first end.

公开(公告)号：US20240064950A1

公开(公告)日：2024-02-22

申请号：US17890762

申请日：2022-08-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jui-Lin Chen ,  Kian-Long Lim ,  Feng-Ming Chang ,  Yi-Feng Ting ,  Hsin-Wen Su ,  Lien-Jung Hung ,  Ping-Wei Wang

IPC: H01L27/11

CPC classification number: H01L27/1104

Abstract: A semiconductor device includes a first source/drain feature on a front side of a substrate. The device includes a first backside metal line under the first source/drain feature and extending lengthwise along a first direction. The device includes a first backside via disposed between the first source/drain feature and the first backside metal line. The first backside metal line is a first bit line of a first static random access memory (SRAM) cell and is connected to the first source/drain feature through the first backside via. The first backside metal line includes a first portion and a second portion each extending widthwise along a second direction perpendicular to the first direction, the first portion is wider than the second portion, and the first portion partially lands on the first backside via. The first and the second portions are substantially aligned on one side along the first direction.

公开(公告)号：US20230411216A1

公开(公告)日：2023-12-21

申请号：US18362163

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien-Jung Hung

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823431 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L21/823821 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/66742 ,  H01L21/823481 ,  H01L21/823412

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US20220344484A1

公开(公告)日：2022-10-27

申请号：US17548133

申请日：2021-12-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Hsuan Chen ,  Ping-Wei Wang

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/265 ,  H01L21/308 ,  H01L29/40

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.