Invention Application
- Patent Title: CRYSTALLIZATION TEMPERATURE REDUCTION OF HIGH-K DIELECTRIC LAYER
-
Application No.: US18328502Application Date: 2023-06-02
-
Publication No.: US20240405093A1Publication Date: 2024-12-05
- Inventor: Shen-Yang LEE , Hsiang-Pi CHANG , Huang-Lin CHAO , Pinyen LIN
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/51
- IPC: H01L29/51 ; H01L21/3115 ; H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/775

Abstract:
The present disclosure describes forming a crystalline high-k dielectric layer at a reduced crystallization temperature in a semiconductor device. The method includes forming a channel structure on a substrate, forming an interfacial layer on the channel structure, forming a first high-k dielectric layer on the interfacial layer, forming dipoles in the first high-k dielectric layer with a dopant, and forming a second high-k dielectric layer on the first high-k dielectric layer. The dopant includes a first metal element. The second high-k dielectric layer includes a second metal element different from the first metal element.
Information query
IPC分类: