The memory is formed of an array of cells, each of which is coupled to the word and bit lines. Each cell comprises only a bipolar transistor coupled to a capacitor. The base terminal of the transistor is connected directly to the word line and either the emitter terminal or the collector terminal of the transistor may be coupled in series with the capacitor. In one embodiment the transistor, in series with the capacitor, is connected between a bit/sense line and a reference voltage and in another embodiment between the bit line and a sense line. Information is stored in the capacitor by discharing the capacitor through the transistor and information is read out by charging the capacitor. During a read/erase operation the word line, which is normally at a quiescent voltage, is raised to a higher voltage to render the transistor conductive between its collector and emitter. Simultaneously, the bit line has impressed upon it a positive voltage. During a write operation the word line has impressed upon it a voltage which is between its quiescent voltage and its read/erase voltage. If a 0 is to be stored, the bit line is maintained at a high level and the capacitor charged. If a 1 is to be stored, the voltage on the bit line is substantially reduced so that the capacitor is discharged. During the read operations a signal is transmitted to the bit line if a 1 has been stored previously.