公开(公告)号：US3621302A

公开(公告)日：1971-11-16

申请号：US3621302D

申请日：1969-01-15

Applicant: IBM

Inventor： PRICER WILBUR DAVID

IPC: G11C5/06 ,  G11C5/14 ,  G11C11/411 ,  G11C11/414 ,  G11C11/415 ,  H01L27/02 ,  H01L27/10 ,  H03K3/286

CPC classification number: G11C11/411 ,  G11C5/063 ,  G11C5/14 ,  G11C11/414 ,  G11C11/415 ,  H01L27/0229 ,  H01L27/10

Abstract: A single power source is connected to a plurality of parallelconnected storage cells, which are in one of two bistable states, to provide a common constant-current source when the cells are in a standby storage condition and to apply a constant voltage source to increase the power level when the cells are in an active condition.

公开(公告)号：US3876992A

公开(公告)日：1975-04-08

申请号：US46693674

申请日：1974-05-06

Applicant: IBM

Inventor： PRICER WILBUR DAVID

IPC: G11C11/404 ,  G11C11/24 ,  G11C11/40

CPC classification number: G11C11/404

Abstract: The memory is formed of an array of cells, each of which is coupled to the word and bit lines. Each cell comprises only a bipolar transistor coupled to a capacitor. The base terminal of the transistor is connected directly to the word line and either the emitter terminal or the collector terminal of the transistor may be coupled in series with the capacitor. In one embodiment the transistor, in series with the capacitor, is connected between a bit/sense line and a reference voltage and in another embodiment between the bit line and a sense line. Information is stored in the capacitor by discharing the capacitor through the transistor and information is read out by charging the capacitor. During a read/erase operation the word line, which is normally at a quiescent voltage, is raised to a higher voltage to render the transistor conductive between its collector and emitter. Simultaneously, the bit line has impressed upon it a positive voltage. During a write operation the word line has impressed upon it a voltage which is between its quiescent voltage and its read/erase voltage. If a 0 is to be stored, the bit line is maintained at a high level and the capacitor charged. If a 1 is to be stored, the voltage on the bit line is substantially reduced so that the capacitor is discharged. During the read operations a signal is transmitted to the bit line if a 1 has been stored previously.

公开(公告)号：US3882467A

公开(公告)日：1975-05-06

申请号：US42688973

申请日：1973-12-20

Applicant: IBM

Inventor： PRICER WILBUR DAVID

IPC: G11C11/402 ,  G11C11/406 ,  G11C11/412 ,  G11C11/417 ,  H01L21/822 ,  H01L27/04 ,  H03K3/356 ,  H03K17/00 ,  H03K17/24 ,  G11C11/40

CPC classification number: G11C11/417 ,  G11C11/4023 ,  G11C11/406 ,  G11C11/412 ,  H03K3/356 ,  H03K3/356052 ,  H03K3/356104 ,  H03K17/24 ,  H03K2217/0036

Abstract: A complementary MOS field effect transistor memory cell is described in which only four devices are interconnected to form a DC stable non-destructive readout circuit. Power consumption during the quiescent, or standby, state is minimum, being limited only by parasitic leakage current. High performance with minimum geometry are provided through the use of a variable source-tosubstrate bias which allows field effect devices to operate in enhancement and depletion mode during standby and selection times, respectively. An array of the cells may be arranged in a word-organized memory.

公开(公告)号：US3641516A

公开(公告)日：1972-02-08

申请号：US3641516D

申请日：1969-09-15

Applicant: IBM

Inventor： CASTRUCCI PAUL P ,  GATES HARLAN R ,  HENLE ROBERT A ,  PRICER WILBUR DAVID ,  MORTON ROBERT M ,  MASON JOHN W ,  NORTH WILLIAM D

IPC: F22B21/06 ,  G11C17/06 ,  G11C17/14 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L27/102 ,  G11C11/36 ,  G11C17/00

CPC classification number: H01L27/1021 ,  F22B21/065 ,  G11C17/06 ,  G11C17/16 ,  H01L23/525 ,  H01L27/00 ,  H01L2924/0002 ,  Y10S148/055 ,  Y10S257/926 ,  H01L2924/00

Abstract: A read only memory having the capability of being written into once after manufacture. The cells of the memory are capable of being fused or permanently altered by directing a fusing current to the selected cells. The cell is a monolithic semiconductor device comprising a diode to be biased in a forward direction and a diode to be biased in the reverse direction structured so as to form back-to-back diodes. The reverse diode has a lower reverse breakdown voltage than the forward diode, and a metal connection, unconnected to any remaining circuit elements contacts the semiconductor device between diode junctions. The fusing current causes a metal-semiconductor alloy to form and short out the reverse diode.

Abstract translation: 一种只读存储器，具有在制造后被写入一次的能力。 存储器的单元能够通过将熔化电流引导到所选择的单元来融合或永久地改变。 电池是一个单片半导体器件，它包括一个正向偏置的二极管和一个反向偏置的二极管，以便形成背对背二极管。 反向二极管具有比正向二极管更低的反向击穿电压，并且未连接到任何剩余的电路元件的金属连接接触二极管接头之间的半导体器件。 熔断电流使金属半导体合金形成并短路反向二极管。