发明授权
- 专利标题: Gate circuit
- 专利标题(中): 门电路
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申请号: US712668申请日: 1976-08-09
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公开(公告)号: US4110634A公开(公告)日: 1978-08-29
- 发明人: Yukuya Tokumaru , Masanori Nakai
- 申请人: Yukuya Tokumaru , Masanori Nakai
- 申请人地址: JP Tokyo
- 专利权人: Tokyo Shibaura Electric Co., Ltd.
- 当前专利权人: Tokyo Shibaura Electric Co., Ltd.
- 当前专利权人地址: JP Tokyo
- 优先权: JP50-96787 19750809; JP51-96786 19760809
- 主分类号: H01L27/02
- IPC分类号: H01L27/02 ; H03K19/084 ; H03K19/091 ; H03K19/08 ; H03K19/20
摘要:
A gate circuit is constituted by a plurality of logical elements formed on the same P type semiconductor substrate. Each logical element is composed of an N type first region and P type second region formed by double diffusion in one of a plurality of P type isolated islands formed on a P type semiconductor substrate, and an N type isolating region and N type buried region surrounding the islands. The P type second region, N type first region and P type island constitute a first vertical PNP transistor by operating as an emitter, base and collector, respectively, while the N type first region, P type island and N type buried region constitute a second vertical NPN transistor by operating as an emitter, base and collector, respectively. In the plurality of logical elements, a Schottky diode is provided for each input section thereof. Connected to a connection point between an anode of this Schottky diode and a base of the second vertical NPN transistor of one logical element is a collector of that of another logical element. A collector of the second NPN transistor of one logical element constitutes an output section.
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