公开(公告)号：US08373442B2

公开(公告)日：2013-02-12

申请号：US13238095

申请日：2011-09-21

申请人： Tomohiro Tanaka

发明人： Tomohiro Tanaka

IPC分类号： G11C8/00 ,  H03K19/084

CPC分类号： G11C8/08 ,  G11C8/10 ,  H03K17/56 ,  H03K17/693 ,  H03K19/096 ,  H03K19/0963

摘要： A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

摘要翻译： 选择器电路包括多个第一选择电路，每个第一选择电路被配置为基于第一选择控制信号选择多个输入信号中的一个，并输出第一输出信号和第二选择电路，其被配置为选择第一输出信号之一 第二选择控制信号的基础。 每个第一选择电路包括充电电路，其被配置为通过在第一周期中将第一节点电连接到第一电压来对第一节点进行充电;以及放电控制电路，被配置为基于第一选择控制信号， 所述输入信号和所述第二选择控制信号是否在所述第一周期之后的第二周期期间通过将所述第一节点电连接到具有低于所述第一电压源的电位的第二电压源来对所充电的第一节点进行放电。

公开(公告)号：US20110140736A1

公开(公告)日：2011-06-16

申请号：US12968154

申请日：2010-12-14

申请人： Lane D. Yoder

发明人： Lane D. Yoder

IPC分类号： H03K19/084 ,  G11C8/10

CPC分类号： G06N3/063 ,  G06N3/0436 ,  G11C8/10

摘要： Logic circuits provide networks to simulate the functions of neural networks of the brain, and can discriminate degrees of state, and combinations of degrees of state, corresponding to a number of neurons. Logic circuits comprise Recursive AND NOT Conjunctions (RANCs), or AND NOT gates. A RANC is a general logic circuit that performs conjunctions for 2n possible combinations of truth values of n propositions. The RANCs function dynamically, with capabilities of excitation and inhibition. Networks of RANCs are capable of subserving a variety of brain functions, including creative and analytical thought processes. A complete n-RANC produces all conjunctions corresponding to the 2n possible combinations of truth values of n propositions.

摘要翻译： 逻辑电路提供网络来模拟大脑的神经网络的功能，并且可以区分对应于多个神经元的状态程度和状态的组合。 逻辑电路包括递归和非连接（RANC）或或非门。 RANC是对n个命题的真值的2n个可能组合执行连接的通用逻辑电路。 RANC具有动态功能，具有激励和抑制能力。 RANC的网络能够服务于各种脑功能，包括创造性和分析思维过程。 完整的n-RANC产生对应于n个命题的真值的2n个可能组合的所有连接。

公开(公告)号：US07535251B2

公开(公告)日：2009-05-19

申请号：US11852032

申请日：2007-09-07

申请人： Chikayoshi Morishima ,  Tokuya Osawa ,  Masaru Haraguchi ,  Yoshihiro Yamashita

发明人： Chikayoshi Morishima ,  Tokuya Osawa ,  Masaru Haraguchi ,  Yoshihiro Yamashita

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0175 ,  H03K19/084 ,  G11C8/00

CPC分类号： H03K19/0005 ,  H03K19/018578

摘要： There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.

摘要翻译： 提供了一种包括输出缓冲电路的半导体器件，其减少用于阻抗调整的电路占据的面积，并允许高速阻抗调节。 在阻抗测量电路中，测量与构成输出缓冲电路的多个晶体管尺寸相同尺寸的参考晶体管的尺寸相等的阻抗值。 基于来自阻抗测量电路的测量结果，阻抗代码产生电路将对应于参考晶体管的阻抗值的阻抗代码输出到输出缓冲器代码产生电路。 输出缓冲器代码产生电路通过执行算术运算处理产生用于调节输出缓冲器电路的阻抗的输出缓冲器代码，以提供基于阻抗代码的物镜阻抗。

公开(公告)号：US5838169A

公开(公告)日：1998-11-17

申请号：US713881

申请日：1996-09-17

申请人： Eric Bernard Schorn

发明人： Eric Bernard Schorn

IPC分类号： H03K19/096 ,  H03K19/084

CPC分类号： H03K19/0963

摘要： A logic block comprised of several transistors is provided. The logic block has several inputs and an output for communicating the result of its logic operation. A precharge device having a clock input is connected to the output of the logic block. The precharge device periodically allows the output of the logic block to become valid. This is accomplished by holding the output of the logic block at a fixed voltage level when the clock input is at a first voltage level, and when the clock input changes to a second voltage level, the precharge device allows the result of the logic function performed by the logic block to appear at the output of the logic block. Also, a charge redistribution prevention device is connected to at least one of the transistors included in the logic block. The charge redistribution prevention device prevents charge redistribution by applying a voltage to at least one of the transistors in the logic block. Applying a voltage in this manner equalizes the difference in voltage between internal nodes of the logic block and the output of the logic block, thereby preventing charge from redistributed.

摘要翻译： 提供由几个晶体管组成的逻辑块。 逻辑块具有多个输入和用于传达其逻辑运算结果的输出。 具有时钟输入的预充电装置连接到逻辑块的输出。 预充电装置周期性地允许逻辑块的输出变为有效。 这通过在时钟输入处于第一电压电平时将逻辑块的输出保持在固定电压电平来实现，并且当时钟输入变为第二电压电平时，预充电装置允许执行逻辑功能的结果 由逻辑块出现在逻辑块的输出端。 此外，电荷再分布防止装置连接到包括在逻辑块中的至少一个晶体管。 电荷再分布防止装置通过向逻辑块中的至少一个晶体管施加电压来防止电荷再分配。 以这种方式施加电压使逻辑块的内部节点与逻辑块的输出之间的电压差相等，从而防止重新分配电荷。

公开(公告)号：US5764085A

公开(公告)日：1998-06-09

申请号：US904244

申请日：1997-07-31

申请人： Ashok Kumar

发明人： Ashok Kumar

IPC分类号： H03K19/0948 ,  H03K19/173 ,  H03K19/084 ,  H03K19/094

CPC分类号： H03K19/1731 ,  H03K19/0948

摘要： Method and apparatus for exploiting exclusivity of operation between a plurality of logic gates. The apparatus comprises a circuit having a plurality of logic gates. Each logic gate comprises a unique control input, and shares a data input with each of the plurality of logic gates. Control signals received at the control inputs insure exclusivity of operation between the logic gates. The shared data input is coupled to a shared fet which may serve as a virtual power supply for each of the plurality of logic gates.

摘要翻译： 用于利用多个逻辑门之间的操作排他性的方法和装置。 该装置包括具有多个逻辑门的电路。 每个逻辑门包括唯一的控制输入，并且与多个逻辑门中的每一个共享与数据输入的数据。 在控制输入端接收的控制信号确保逻辑门之间的操作排他性。 共享数据输入耦合到可以用作多个逻辑门中的每一个的虚拟电源的共享的fet。

公开(公告)号：US5646558A

公开(公告)日：1997-07-08

申请号：US534598

申请日：1995-09-27

申请人： Shahram Jamshidi

发明人： Shahram Jamshidi

IPC分类号： H03K17/00 ,  H03K17/693 ,  H03K19/084 ,  H03K19/094

CPC分类号： H03K17/693 ,  H03K17/005

摘要： A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.

摘要翻译： 复用布置。 多路复用布置包括一组数据输入，其中第一多路复用器耦合到该组数据输入的第一子集，第二多路复用器耦合到该组数据输入的第二子集。 选择第一和第二多路复用器中的一个在任何给定时间通过该组数据输入中的一个。 逻辑门耦合到第一和第二数据输出，并且逻辑门响应于由第一和第二多路复用器输出的值合成用于复用装置的输出信号，使得多路复用布置作为单个复用器工作。 根据一个实施例，未选择传递数据的多路复用器的输出偏置到已知状态。

公开(公告)号：US5546024A

公开(公告)日：1996-08-13

申请号：US475453

申请日：1995-06-07

申请人： Craig B. Greenberg

发明人： Craig B. Greenberg

IPC分类号： G11C8/10 ,  H03K19/096 ,  H03K19/084

CPC分类号： G11C8/10 ,  H03K19/0963

摘要： A NOR decode circuit which includes a latch composed of a pair of n-channel transistors and a pair of p-channel transistors with the p-channel transistor of one latch portion coupled to a reference circuit transistor via a first pass transistor and the p-channel transistor of the other latch portion coupled to the address select line controlled transistors via a second pass transistor. The pass transistors are also controlled by an enable row (ENROW) signal. The address transistors are larger and conduct more current than the reference transistor. When ENROW is activated, the n-channel transistors of the latch are enabled and current passes through one side of the latch circuit and through a third transistor in parallel with the address transistors if any of the address transistors are turned on. Current also flows through the other side of the latch circuit and through a fourth transistor in parallel with the reference transistor. The second pass transistor conducts a current I.sub.1 plus the current through the reference transistor (I.sub.ref) and the first pass transistor conducts a current I.sub.1 plus the current through an address transistor (nI.sub.ref). Therefore, the second pass transistor conducts a current I.sub.1 +I.sub.ref and the first pass transistor conducts a current I.sub.1 +nI.sub.ref. The difference between these currents, i.e. (n-1)I.sub.ref, is amplified by the latch, causing the row line to remain low when an address transistor is selected and causing the row line to be high when none of the address transistors is selected.

摘要翻译： 一种NOR解码电路，其包括由一对n沟道晶体管和一对p沟道晶体管组成的锁存器，其中一个锁存部分的p沟道晶体管经由第一传输晶体管耦合到参考电路晶体管， 通过第二传输晶体管耦合到地址选择线控制的晶体管的另一个锁存部分的通道晶体管。 传输晶体管也由使能行（ENROW）信号控制。 地址晶体管较大并且导通比参考晶体管更多的电流。 当ENROW被激活时，如果任何地址晶体管导通，则锁存器的n沟道晶体管被使能，并且电流通过锁存电路的一侧并通过与地址晶体管并联的第三晶体管。 电流也流过锁存电路的另一侧并通过与参考晶体管并联的第四晶体管。 第二传输晶体管导通电流I1加上通过参考晶体管（Iref）的电流，第一传输晶体管导通电流I1加上通过地址晶体管（nIref）的电流。 因此，第二传输晶体管导通电流I1 + Iref，第一传输晶体管导通电流I1 + nIref。 这些电流之间的差异，即（n-1）Iref，被锁存器放大，当选择地址晶体管时，使行线保持低电平，并且当没有选择地址晶体管时，使行线为高电平。

公开(公告)号：US5534810A

公开(公告)日：1996-07-09

申请号：US366295

申请日：1994-12-28

申请人： Charles M. White

发明人： Charles M. White

IPC分类号： G09G1/00 ,  H03F1/30 ,  H03F3/30 ,  H04N3/32 ,  H03K19/084 ,  H03K19/094

CPC分类号： H03F1/307 ,  H03F3/3066 ,  H03F3/3076 ,  H04N3/32

摘要： A driver circuit especially for driving scan velocity modulation (SVM) coils or similar loads is characterized by low quiescent current loading and high peak output. The driver is coupled to an input signal varying between a quiescent signal level and a peak signal level. A transistor is coupled to a power supply and to the input signal, so as to conduct according to the input signal. A nonlinear element such as a diode is coupled in series with the emitter-collector junction of the transistor, and is biased to a voltage slightly less than a forward biased conducting diode voltage drop. Thus the diode has a higher resistance when the transistor is conducting at the quiescent signal level, and a lower resistance when the transistor is conducting at the peak signal level. The quiescent bias conditions are maintained by resistors in series and parallel with the diode. The driver may be configured as a complementary push-pull stage.

摘要翻译： 特别适用于驱动扫描速度调制（SVM）线圈或类似负载的驱动电路的特点是低静态电流负载和高峰值输出。 驱动器耦合到在静态信号电平和峰值信号电平之间变化的输入信号。 晶体管耦合到电源和输入信号，以便根据输入信号进行导通。 诸如二极管的非线性元件与晶体管的发射极 - 集电极结串耦合，并被偏置到略小于正向偏置的导通二极管压降的电压。 因此，当晶体管以静态信号电平导通时，二极管具有较高的电阻，并且当晶体管以峰值信号电平导通时，二极管具有较高的电阻。 静态偏置条件由电阻串联并联，与二极管并联。 驱动器可以被配置为互补的推挽级。

公开(公告)号：US5521558A

公开(公告)日：1996-05-28

申请号：US333739

申请日：1994-11-03

申请人： Wilhelm Wilhelm ,  Dirk Friedrich

发明人： Wilhelm Wilhelm ,  Dirk Friedrich

IPC分类号： H03K3/282 ,  H03K3/012 ,  H03K3/03 ,  H03K19/013 ,  H03K19/086 ,  H03K19/084 ,  H03B5/02

CPC分类号： H03K3/012 ,  H03K19/086 ,  H03K3/0315 ,  H03K3/0322

摘要： An inverter stage includes a supply voltage terminal and a reference potential terminal. An npn transistor has a base terminal for receiving an input signal, a collector terminal for supplying an output signal, and an emitter terminal. A controllable current source is connected between the emitter terminal of the transistor and the reference potential terminal. A series circuit of at least two diodes is connected between the supply voltage terminal and the collector terminal of the transistor. A symmetrical inverter stage assembly includes two of the inverter stages being connected in parallel with the emitters of the transistors of each of the inverter stages being connected to one another. A ring oscillator includes n (n.gtoreq.1) of the inverter stages connected in series. The inverter stages include first and last inverter stages, each of the inverter stages has an output and an input, and the output of the last inverter stage is connected to the input of the first inverter stage.

摘要翻译： 逆变器级包括电源电压端子和参考电位端子。 npn晶体管具有用于接收输入信号的基极端子，用于提供输出信号的集电极端子和发射极端子。 可控电流源连接在晶体管的发射极端子和参考电位端子之间。 至少两个二极管的串联电路连接在晶体管的电源电压端子和集电极端子之间。 对称的逆变器级组件包括两个反相级并联连接，每个逆变器级的晶体管的发射极彼此连接。 环形振荡器包括串联连接的逆变器级的n（n> / = 1）。 逆变器级包括第一和最后的反相器级，每个反相器级具有输出和输入，并且最后的反相器级的输出端连接到第一反相器级的输入端。

公开(公告)号：US5467050A

公开(公告)日：1995-11-14

申请号：US177811

申请日：1994-01-04

申请人： John S. Clapp, III ,  Wayne T. Chen

发明人： John S. Clapp, III ,  Wayne T. Chen

IPC分类号： H01L27/04 ,  G05F3/20 ,  H01L21/822 ,  H03K17/082 ,  H03K19/096 ,  G05F1/10 ,  H03K5/08 ,  H03K19/084

CPC分类号： G05F3/205 ,  H03K17/0822

摘要： A dynamic biasing circuit is disclosed that includes a blocking current source (20) having a first current path connected to a first node (NODE 1) and a second current path connected to a second node (NODE 3). A linear source follower (22) has a first current path connected to the second node (NODE 3), a second current path connected to a voltage reference (24), and an input connected to the first node (NODE 1). A parasitic capacitor (26) is connected to the first node (NODE 1) and to ground potential, and a parasitic capacitor (28) is connected to the second node (NODE 3) and to ground potential.

摘要翻译： 公开了一种动态偏置电路，其包括具有连接到第一节点（NODE 1）的第一电流路径和连接到第二节点（NODE 3）的第二电流路径）的阻塞电流源（20）。 线性源极跟随器（22）具有连接到第二节点（NODE 3）的第一电流路径，连接到电压基准（24）的第二电流路径和连接到第一节点（NODE 1）的输入）。 寄生电容器（26）连接到第一节点（NODE 1）和接地电位，寄生电容器（28）连接到第二节点（NODE 3）和接地电位。