发明授权
- 专利标题： Logic circuit with two pairs of cross-coupled NAND/NOR gates
- 专利标题（中）： 具有两对交叉耦合的NAND /非门的逻辑电路
-
申请号： US859130申请日： 1977-12-09
-
公开(公告)号： US4160173A公开(公告)日： 1979-07-03
- 发明人: Kiyoshi Aoki
- 申请人： Kiyoshi Aoki
- 申请人地址： JPX Kawasaki
- 专利权人： Tokyo Shibaura Electric Co., Ltd.
- 当前专利权人： Tokyo Shibaura Electric Co., Ltd.
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX51-150199 19761214; JPX51-150203 19761214; JPX52-6838 19770126; JPX52-6840 19770126
- 主分类号： H03K3/288
- IPC分类号： H03K3/288 ; H03K3/286 ; H03K19/08 ; H03K19/20 ; H03K21/00
摘要：
A logic circuit provided with first and second cross-coupled NAND/NOR gates and third and fourth cross-coupled NAND/NOR gates. The second NAND/NOR gate is arranged to have a delay of output variation longer than that of the first NAND/NOR gate. A desired logic input signal is applied to one input of the first NAND/NOR gate. A first clock pulse is applied to the first and second NAND/NOR gates. A second clock pulse of opposite polarity to the first clock is applied to the fourth NAND/NOR gate. The output of the first NAND/NOR gate is coupled with the input of the third NAND/NOR gate.
公开/授权文献
- US5157833A Method for manufacturing tape guide for use in data cartridge 公开/授权日：1992-10-27
信息查询
IPC分类:
