发明授权
US4315201A Alignment apparatus for mask and wafer used in manufacturing
semiconductor circuit elements
失效
用于制造半导体电路元件的掩模和晶片的对准装置
- 专利标题: Alignment apparatus for mask and wafer used in manufacturing semiconductor circuit elements
- 专利标题(中): 用于制造半导体电路元件的掩模和晶片的对准装置
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申请号: US884534申请日: 1978-03-08
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公开(公告)号: US4315201A公开(公告)日: 1982-02-09
- 发明人: Akiyoshi Suzuki , Ryozo Hiraga , Ichiro Kano , Hideki Yoshinari , Masao Totsuka , Yuzo Kato , Yasuo Ogino
- 申请人: Akiyoshi Suzuki , Ryozo Hiraga , Ichiro Kano , Hideki Yoshinari , Masao Totsuka , Yuzo Kato , Yasuo Ogino
- 申请人地址: JPX Tokyo
- 专利权人: Canon Kabushiki Kaisha
- 当前专利权人: Canon Kabushiki Kaisha
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX54/26304 19770310
- 主分类号: H01L21/30
- IPC分类号: H01L21/30 ; G03F9/00 ; H01L21/027 ; H01L21/67 ; H01L21/68 ; G05B1/06
摘要:
An alignment apparatus for mask and wafer each having alignment marks provided in a narrow strip like area between circuit patterns is disclosed, which mask and wafer are used in manufacturing semiconductor circuit elements. In the apparatus, the mask and wafer are scanned to obtain scan signals by means of which the amount of relative deviation between the alignment marks on mask and wafer is detected. By means of the detected signal, an alignment is effected between the mask and wafer in the apparatus. For this type of alignment apparatus, there is a problem that since the alignment marks are provided in the narrow strip like area, no coincidence between the scanning position and the strip area is attainable with pre-alignment accuracy. Improvement in the alignment apparatus according to the invention lies in that a reading of alignment marks is initiated after the coincidence is photoelectrically detected.
公开/授权文献
- US5921131A Method for frictionally guiding and forming ferrous metal 公开/授权日:1999-07-13
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