发明授权
- 专利标题: Directory test error mode control apparatus
- 专利标题(中): 目录测试错误模式控制装置
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申请号: US509825申请日: 1983-06-30
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公开(公告)号: US4562536A公开(公告)日: 1985-12-31
- 发明人: James W. Keeley , Robert V. Ledoux , Virendra S. Negi
- 申请人: James W. Keeley , Robert V. Ledoux , Virendra S. Negi
- 申请人地址: MA Waltham
- 专利权人: Honeywell Information Systems Inc.
- 当前专利权人: Honeywell Information Systems Inc.
- 当前专利权人地址: MA Waltham
- 主分类号: G06F11/00
- IPC分类号: G06F11/00 ; G06F11/10 ; G06F11/267 ; G06F12/08 ; G06F12/12 ; G11C29/00 ; G11C29/02 ; G06F13/00
摘要:
A multilevel set associative cache system whose directory and cache store organized into levels of memory locations. Round robin replacement apparatus is used to identify in which level information is to be replaced. The directory includes error checking apparatus for generating address check bits which are written into directory locations together with addresses. Control apparatus in response to error signals from the error checking apparatus degrades cache operation to those levels detected to be free from errors. Test error mode control apparatus which couples to the replacement and check bit apparatuses causes the address check bits to be selectively forced to incorrect values in response to commands received from a central processing unit enabling the verification of both the checking and control apparatus without interference from other operations initiated by the central processing unit.
公开/授权文献
- US5611974A Method for preparing or repairing a machine foundation 公开/授权日:1997-03-18
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