公开(公告)号：US08116330B2

公开(公告)日：2012-02-14

申请号：US12475838

申请日：2009-06-01

申请人： James W. Keeley ,  Douglas E. Sanders ,  Andrew Hyonil Chong

发明人： James W. Keeley ,  Douglas E. Sanders ,  Andrew Hyonil Chong

IPC分类号： H04L12/56

CPC分类号： G06F13/404

摘要： Apparatus and methods for an enhanced bridge device for coupling multiple non-Fiber Channel storage devices to a Fiber Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.

摘要翻译： 用于将多个非光纤通道存储设备耦合到光纤通道仲裁环（FC-AL）通信介质的增强桥接设备的装置和方法。 其特征和方面提供了用于处理环路端口旁路（LPB）和环路端口使能（LPE）原语序列的FC-AL增强电路，寻址到与桥耦合的存储设备相关联的任何目标仲裁环物理地址（T-ALPA） 而不考虑由桥接设备处理并与与桥接设备耦合的其他存储设备相关联的其他T-ALPA的当前旁路/非旁路状态。

公开(公告)号：US5664200A

公开(公告)日：1997-09-02

申请号：US414983

申请日：1995-03-31

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F13/26 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F13/18

CPC分类号： G06F13/24 ,  G06F13/26 ,  G06F15/17

摘要： A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request. Each interrupt mechanism further includes interrupt retry means containing a refused interrupt register means for storing the channel address of the processor generating the not acknowledge in response and the priority level code contained in the interrupt request, and a level monitor logic unit connected to the system bus. The level monitor logic unit detects interrupt completed commands and compares the channel address and priority level code in the interrupt completed command to channel address and level code stored in the refused interrupt register means. When the processor channel addresses match and the level code is less than the level stored in the refused interrupt register means, the monitor logic unit generates a retry interrupt output. The processor retries the corresponding previously refused interrupt request upon receipt of the retry interrupt output.

摘要翻译： 多处理器计算机系统包括多个处理器，每个处理器具有中断机制并且共同连接到通过其传送中断请求的系统总线。 当处理器接受另一个处理器的中断请求时，它会在系统总线上产生一个确认响应。 如果这样的处理器包含等于或更高优先级的先前和未决的中断请求，它将在系统总线上产生不确认响应并拒绝中断请求。 在完成对中断请求的服务的完成时，每个处理器放置在系统总线上，一个中断完成命令，包括一个标识这样的处理器的地址，一个指定其所切换的优先级的代码，以及一个指示处理器完成服务的代码 中断请求。 每个中断机制还包括中断重试装置，其中包含一个拒绝中断寄存器装置，用于存储响应中产生不应答的处理器的通道地址以及中断请求中包含的优先级代码，以及连接到系统总线的电平监视逻辑单元 。 电平监视逻辑单元检测中断完成命令，并将中断完成命令中的通道地址和优先级代码与存储在拒绝中断寄存器装置中的通道地址和电平代码进行比较。 当处理器通道地址匹配并且电平代码小于存储在拒绝中断寄存器装置中的电平时，监视器逻辑单元产生重试中断输出。 接收到重试中断输出后，处理器重试相应的先前拒绝的中断请求。

公开(公告)号：US5446847A

公开(公告)日：1995-08-29

申请号：US531

申请日：1993-01-04

申请人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

发明人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

IPC分类号： G06F13/372 ,  G06F13/18

CPC分类号： G06F13/372

摘要： A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.

摘要翻译： 总线接口优先级网络通过多个不同类型的请求者提供对系统总线的访问，作为它们需要处理的事务的类型的函数。 该网络包括用于识别请求者的类型的可编程电路，并且基于请求者类型选择访问系统总线的延迟，从而消除了对最慢请求者调整定时的需要。

公开(公告)号：US5341495A

公开(公告)日：1994-08-23

申请号：US771297

申请日：1991-10-04

申请人： Thomas F. Joyce ,  James W. Keeley ,  Richard A. Lemay ,  Bruno DiPlacido, Jr. ,  Martin M. Massucci

发明人： Thomas F. Joyce ,  James W. Keeley ,  Richard A. Lemay ,  Bruno DiPlacido, Jr. ,  Martin M. Massucci

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/4027

摘要： A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

摘要翻译： 处理单元紧密地耦合到利用分离循环总线协议的系统总线，并且包括可以从这种总线访问的本地存储器。 本地存储器耦合到根据预定总线协议操作的高速同步总线。 处理单元包括耦合到高速同步总线和异步系统总线的状态机。 状态机在从使用分离周期协议的系统总线传送发给本地存储器的命令时模拟预定的总线同步协议。

公开(公告)号：US4839800A

公开(公告)日：1989-06-13

申请号：US901847

申请日：1986-08-29

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F13/26

CPC分类号： G06F13/26

摘要： A multiprocessor system includes a number of subsystems all coupled in common to an asynchronous system bus. Apparatus is included in the system bus interface logic of each processing subsystem to receive commands from the system bus and compare the interrupt priority level of the new command with the current command being executed. If the new command has a lower interrupt priority than the current command, then the subsystem sending the command will receive a not acknowledge response from the processing system. The apparatus is responsive to certain control signals from the new command to bypass the interrupt priority comparison logic and initiate an immediate interrupt regardless of the interrupt priority level of the current command being executed by the processing subsystem. The processing subsystem may also generate a command to itself via the system bus which requires the high speed interrupt.

摘要翻译： 多处理器系统包括多个子系统，所有子系统共同连接到异步系统总线。 装置包括在每个处理子系统的系统总线接口逻辑中，以从系统总线接收命令，并将新命令的中断优先级与正在执行的当前命令进行比较。 如果新命令的中断优先级低于当前命令，则发送命令的子系统将从处理系统接收到未确认的响应。 该装置响应于来自新命令的某些控制信号绕过中断优先级比较逻辑并且启动立即中断，而不管处理子系统正在执行的当前命令的中断优先级。 处理子系统还可以经由需要高速中断的系统总线对其自身产生命令。

公开(公告)号：US4785395A

公开(公告)日：1988-11-15

申请号：US879864

申请日：1986-06-27

申请人： James W. Keeley

发明人： James W. Keeley

IPC分类号： G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0855 ,  G06F12/084

摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units. For completely independent operation, each processing unit is allocated one-half of the total available cache memory space by separate accounting replacement apparatus included within the buffer memory stage. A multiple allocation memory (MAM) is also included in the buffer memory stage. During each directory allocation cycle performed for a processing unit, the allocated space of the other processing unit is checked for the presence of a multiple allocation. The address of the multiple allocated location associated with the processing unit having the lower priority is stored in the MAM allowing for earliest data replacement thereby maintaining data coherency between both independently operated processing units.

摘要翻译： 缓存存储器子系统具有由至少一对独立操作的中央处理单元共享的多级目录存储器和缓冲存储器流水线级。 为了完全独立的操作，每个处理单元通过包括在缓冲存储器级内的单独的计费替换装置分配总可用高速缓冲存储器空间的一半。 多分配存储器（MAM）也包括在缓冲存储器级中。 在对处理单元执行的每个目录分配周期期间，检查其他处理单元的分配空间以存在多个分配。 与具有较低优先级的处理单元相关联的多个分配位置的地址被存储在MAM中，允许最早的数据替换，从而维持两个独立操作的处理单元之间的数据一致性。

公开(公告)号：US4695943A

公开(公告)日：1987-09-22

申请号：US655473

申请日：1984-09-27

申请人： James W. Keeley ,  Thomas F. Joyce

发明人： James W. Keeley ,  Thomas F. Joyce

IPC分类号： G06F12/08 ,  G06F13/00 ,  G11C7/00

CPC分类号： G06F12/084

摘要： A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.

摘要翻译： 高速缓冲存储器单元被构造成具有可由包括两个独立操作的中央处理单元（CPU）的多个源共享的两级流水线。 包括在高速缓冲存储器单元内的装置用于向两个CPU分配备用时隙，这两个CPU通过流水线阶段来抵消它们的操作。 这允许高速缓冲存储器单元的一个流水线阶段对一个CPU执行目录搜索，而另一个流水线级对另一个CPU执行数据缓冲器读取。 每个CPU被编程为使用少于分配给它的所有时隙。 因此，处理单元无冲突运行，而流水线阶段被释放以处理来自其他来源的请求，例如来自主存储器或高速缓存更新的替换数据。

公开(公告)号：US4667288A

公开(公告)日：1987-05-19

申请号：US509898

申请日：1983-06-30

申请人： James W. Keeley ,  Robert V. Ledoux ,  Virendra S. Negi

发明人： James W. Keeley ,  Robert V. Ledoux ,  Virendra S. Negi

IPC分类号： G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F12/00 ,  G06F12/12 ,  G11C29/00

CPC分类号： G11C29/88 ,  G06F11/073 ,  G06F11/0772 ,  G06F11/2289 ,  G06F12/126 ,  G06F11/10 ,  G06F12/00 ,  G06F2212/1032

摘要： A multilevel set associative cache system whose directory and cache store are organized into levels of memory locations includes control apparatus which selectively degrades cache operation in response to error signals from directory error checking circuits to those levels detected to be free from errors. Test control apparatus which couples to the directory error checking apparatus operates to selectively enable and disable the directory error checking circuits in response to commands received from a central processing unit so as to enable the testing of the cache directory and other portions of the cache system using common test routines.

摘要翻译： 其目录和高速缓存存储器被组织到存储器位置的级别的多级组关联缓存系统包括控制装置，其响应于来自目录错误检查电路的错误信号而选择性地降级高速缓存操作到被检测为没有错误的那些级别。 耦合到目录错误检查装置的测试控制装置操作以响应于从中央处理单元接收的命令选择性地启用和禁用目录错误检查电路，以便能够使用高速缓存系统的高速缓存目录和其他部分的测试 常用测试程序。

公开(公告)号：US4764862A

公开(公告)日：1988-08-16

申请号：US717201

申请日：1985-03-28

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F11/00 ,  G06F13/42 ,  G06F13/14

CPC分类号： G06F13/4213 ,  G06F11/00

摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

摘要翻译： 数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。 每个单元包括用于确认从其他单元接收的请求的响应装置。 多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。 当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。 这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

公开(公告)号：US4724519A

公开(公告)日：1988-02-09

申请号：US750117

申请日：1985-06-28

申请人： George J. Barlow ,  James W. Keeley ,  Elmer W. Carroll

发明人： George J. Barlow ,  James W. Keeley ,  Elmer W. Carroll

IPC分类号： G06F13/14 ,  G06F12/06 ,  G06F13/362 ,  G06F13/368 ,  G06F13/378 ,  G06F13/36

CPC分类号： G06F13/368 ,  G06F12/0623 ,  G06F13/378

摘要： A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.

摘要翻译： 数据处理系统具有系统总线网络，该系统总线网络包括用于在耦合到总线的多个子系统之间异步地传送数据的分布式优先级网络。 每个子系统包括优先级逻辑电路，其被耦合以从优先级网络接收一组优先级信号，该优先级信号建立当子系统具有请求子系统访问总线的最高优先级时。 子系统的数量包括多个相同的子系统，每个子系统具有信道号分配装置。 每个相同子系统的装置被连接以接收该组优先级信号中的至少一个。 在系统总线的空闲状态期间，每个相同子系统的装置操作以存储优先级信号的唯一状态，其被定义为总线上子系统位置的函数，从而为每个相同的子系统自动建立唯一的信道数值 。